Export Zfa ISA extension[1] through hwprobe. Link: https://drive.google.com/file/d/1VT6QIggpb59-8QRV266dEE4T8FZTxGq4/view [1] Signed-off-by: Clément Léger <cleger@xxxxxxxxxxxx> --- Documentation/riscv/hwprobe.rst | 4 ++++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_riscv.c | 1 + 3 files changed, 6 insertions(+) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst index 782ac26cb92a..f81e3c93ac1e 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -154,6 +154,10 @@ The following keys are defined: defined in the RISC-V Vector manual starting from commit e2ccd0548d6c ("Remove draft warnings from Zvfh[min]"). + * :c:macro:`RISCV_HWPROBE_EXT_ZFA`: The Zfa extension is supported as + defined in the RISC-V ISA manual starting from commit 056b6ff467c7 + ("Zfa is ratified"). + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 79407010952a..4014492c3960 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -54,6 +54,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 28) #define RISCV_HWPROBE_EXT_ZVFH (1 << 29) #define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 30) +#define RISCV_HWPROBE_EXT_ZFA (1 << 31) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 8d6edd721627..a6a063f1dcf5 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -192,6 +192,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, if (has_fpu()) { CHECK_ISA_EXT(ZFH); CHECK_ISA_EXT(ZFHMIN); + CHECK_ISA_EXT(ZFA); } #undef CHECK_ISA_EXT } -- 2.42.0
