Export the following scalar crypto extensions through hwprobe:
- Zbkb
- Zbkc
- Zbkx
- Zknd
- Zkne
- Zknh
- Zksed
- Zksh
- Zkt
Signed-off-by: Clément Léger <cleger@xxxxxxxxxxxx>
---
Documentation/riscv/hwprobe.rst | 30 +++++++++++++++++++++++++++
arch/riscv/include/uapi/asm/hwprobe.h | 10 +++++++++
arch/riscv/kernel/sys_riscv.c | 10 +++++++++
3 files changed, 50 insertions(+)
diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst
index a52996b22f75..968895562d42 100644
--- a/Documentation/riscv/hwprobe.rst
+++ b/Documentation/riscv/hwprobe.rst
@@ -77,6 +77,36 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined
in version 1.0 of the Bit-Manipulation ISA extensions.
+ * :c:macro:`RISCV_HWPROBE_EXT_ZBC` The Zbc extension is supported, as defined
+ in version 1.0 of the Scalar Crypto ISA extensions.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZBKB` The Zbkb extension is supported, as
+ defined in version 1.0 of the Scalar Crypto ISA extensions.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZBKC` The Zbkc extension is supported, as
+ defined in version 1.0 of the Scalar Crypto ISA extensions.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZBKX` The Zbkx extension is supported, as
+ defined in version 1.0 of the Scalar Crypto ISA extensions.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZKND` The Zknd extension is supported, as
+ defined in version 1.0 of the Scalar Crypto ISA extensions.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZKNE` The Zkne extension is supported, as
+ defined in version 1.0 of the Scalar Crypto ISA extensions.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZKNH` The Zknh extension is supported, as
+ defined in version 1.0 of the Scalar Crypto ISA extensions.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZKSED` The Zksed extension is supported, as
+ defined in version 1.0 of the Scalar Crypto ISA extensions.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZKSH` The Zksh extension is supported, as
+ defined in version 1.0 of the Scalar Crypto ISA extensions.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZKT` The Zkt extension is supported, as defined
+ in version 1.0 of the Scalar Crypto ISA extensions.
+
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
information about the selected set of processors.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 006bfb48343d..89d0e37a01e9 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -29,6 +29,16 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_EXT_ZBA (1 << 3)
#define RISCV_HWPROBE_EXT_ZBB (1 << 4)
#define RISCV_HWPROBE_EXT_ZBS (1 << 5)
+#define RISCV_HWPROBE_EXT_ZBC (1 << 6)
+#define RISCV_HWPROBE_EXT_ZBKB (1 << 7)
+#define RISCV_HWPROBE_EXT_ZBKC (1 << 8)
+#define RISCV_HWPROBE_EXT_ZBKX (1 << 9)
+#define RISCV_HWPROBE_EXT_ZKND (1 << 10)
+#define RISCV_HWPROBE_EXT_ZKNE (1 << 11)
+#define RISCV_HWPROBE_EXT_ZKNH (1 << 12)
+#define RISCV_HWPROBE_EXT_ZKSED (1 << 13)
+#define RISCV_HWPROBE_EXT_ZKSH (1 << 14)
+#define RISCV_HWPROBE_EXT_ZKT (1 << 15)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index e207874e686e..2b50c661da90 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -162,6 +162,16 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
CHECK_ISA_EXT(ZBA);
CHECK_ISA_EXT(ZBB);
CHECK_ISA_EXT(ZBS);
+ CHECK_ISA_EXT(ZBC);
+ CHECK_ISA_EXT(ZBKB);
+ CHECK_ISA_EXT(ZBKC);
+ CHECK_ISA_EXT(ZBKX);
+ CHECK_ISA_EXT(ZKND);
+ CHECK_ISA_EXT(ZKNE);
+ CHECK_ISA_EXT(ZKNH);
+ CHECK_ISA_EXT(ZKSED);
+ CHECK_ISA_EXT(ZKSH);
+ CHECK_ISA_EXT(ZKT);
#undef CHECK_ISA_EXT
}
--
2.42.0
