From: Haibo Chen <haibo.chen@xxxxxxx>
For original setting, the start point is 20, after the SION setting,
ERR052021 can be workaround, but start point from 20 is too large,
especially for the LD 133MHz case.
Set the tuning start point as 1, tuning step as 2, so that, for the
40 times tuning logic, it can cover 1~81, its large and safe enough
for all different devices like eMMC/SD/SDIO.
Signed-off-by: Haibo Chen <haibo.chen@xxxxxxx>
---
arch/arm64/boot/dts/freescale/imx93.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi
index ceccf4766440..ce76ae9e1856 100644
--- a/arch/arm64/boot/dts/freescale/imx93.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
@@ -874,7 +874,7 @@ usdhc1: mmc@42850000 {
<&clk IMX93_CLK_USDHC1_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <8>;
- fsl,tuning-start-tap = <20>;
+ fsl,tuning-start-tap = <1>;
fsl,tuning-step = <2>;
status = "disabled";
};
@@ -888,7 +888,7 @@ usdhc2: mmc@42860000 {
<&clk IMX93_CLK_USDHC2_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
- fsl,tuning-start-tap = <20>;
+ fsl,tuning-start-tap = <1>;
fsl,tuning-step = <2>;
status = "disabled";
};
@@ -951,7 +951,7 @@ usdhc3: mmc@428b0000 {
<&clk IMX93_CLK_USDHC3_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
- fsl,tuning-start-tap = <20>;
+ fsl,tuning-start-tap = <1>;
fsl,tuning-step = <2>;
status = "disabled";
};
--
2.34.1
