This series intends to address a problem I had when using the Si5351A as
a runtime adjustable audio bit clock. The basic issue is that the driver
in its current form unconditionally resets the PLL whenever adjusting
its rate. But this reset causes an unwanted ~1.4 ms LOW signal glitch in
the clock output.
As a remedy, a new property is added to control the reset behaviour of
the PLLs more precisely. In the process I also converted the bindings to
YAML.
Changes:
v3 -> v4:
- remove spurious | per Rob's suggestion
- simplify conditional clocks/clock-names per Rob's suggestion
- remove mention of clkout[0-7] still being admissible in the commit
body of patch 1 - while the Linux driver still tolerates this, the
new dt-bindings do not
v2 -> v3:
- address further comments from Rob:
- drop unnecessary refs and minItems
- simplify if conditions for chip variants
- ignore his comment about dropping '|', as line would be >80 columns
- move additionalProperties: false close to type: object
- define clocks/clock-names at top-level
- drop patch to dove-cubox dts per Krzysztof's comment - will send
separately
- collect Sebastian's Acked-by
v1 -> v2:
- address Rob's comments on the two dt-bindings patches
- new patch to correct the clock node names in the only upstream device
tree using si5351
---
Alvin Šipraga (3):
dt-bindings: clock: si5351: convert to yaml
dt-bindings: clock: si5351: add PLL reset mode property
clk: si5351: allow PLLs to be adjusted without reset
.../devicetree/bindings/clock/silabs,si5351.txt | 126 ----------
.../devicetree/bindings/clock/silabs,si5351.yaml | 269 +++++++++++++++++++++
drivers/clk/clk-si5351.c | 47 +++-
include/linux/platform_data/si5351.h | 2 +
4 files changed, 315 insertions(+), 129 deletions(-)
---
base-commit: b7c08e5d3824bc57182b308c1e158ddfdbe4cd00
change-id: 20231014-alvin-clk-si5351-no-pll-reset-ecfac0a6550c
