On Thu, Oct 05, 2023 at 11:03:43AM +0200, Christophe ROULLIER wrote: > > On 9/28/23 19:17, Conor Dooley wrote: > > On Thu, Sep 28, 2023 at 05:15:02PM +0200, Christophe Roullier wrote: > > > Add property st,ext-phyclk to manage cases when PHY have no cristal/quartz > > > This property can be used with RMII phy without cristal 50Mhz and when we > > > want to select RCC clock instead of ETH_REF_CLK > > > Can be used also with RGMII phy with no cristal and we select RCC clock > > > instead of ETH_CLK125 > > > This new property replace st,eth-clk-sel and st,eth-ref-clk-sel > > I don't really see a response to Rob's comment on v2, either here or in > > a reply to his email on v2: > > | Certainly 1 property is better than 2 for me, but carrying 3 is not > > | great. I don't understand why the we need a new property. What can't be > > | supported with the existing properties? > > > > A sentence saying explaining exactly what the old properties do not > > support that this one does, would be very helpful. > I understand your remarks, the goal of the new property is to be more simple > for customers/users > > with old properties we have lots of support to explain which one to use in > which cases, now only one property to use (regardless of mode) I'm inclined to say "that's tough" & that the existing property descriptions should be improved rather than adding yet a third one. Maybe you're lucky and Rob disagrees with me :) Thanks, Conor. > > > Signed-off-by: Christophe Roullier <christophe.roullier@xxxxxxxxxxx> > > > --- > > > Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 9 +++++++++ > > > 1 file changed, 9 insertions(+) > > > > > > diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml > > > index ca976281bfc22..67840cab02d2d 100644 > > > --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml > > > +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml > > > @@ -78,12 +78,21 @@ properties: > > > encompases the glue register, the offset of the control register and > > > the mask to set bitfield in control register > > > + st,ext-phyclk: > > > + description: > > > + set this property in RMII mode when you have PHY without crystal 50MHz and want to > > > + select RCC clock instead of ETH_REF_CLK. or in RGMII mode when you want to select > > > + RCC clock instead of ETH_CLK125. > > > + type: boolean > > > + > > > st,eth-clk-sel: > > > + deprecated: true > > > description: > > > set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125. > > > type: boolean > > > st,eth-ref-clk-sel: > > > + deprecated: true > > > description: > > > set this property in RMII mode when you have PHY without crystal 50MHz and want to > > > select RCC clock instead of ETH_REF_CLK. > > > -- > > > 2.25.1 > > >
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