On 16:42-20231004, Nitin Yadav wrote:
> Add gpmc0 and elm0 nodes in k3-am62-main. Add GPMC0_CFG and
s/gpmc0/GPMC and elm0/ELM
Also a oneliner as to what GPMC and ELM are will be helpful.
> GPMC0_DATA entry in cbass_main node.
>
> Signed-off-by: Nitin Yadav <n-yadav@xxxxxx>
> ---
> arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 29 ++++++++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-am62.dtsi | 2 ++
> 2 files changed, 31 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
> index ac760d9b831d..f854369dfc27 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
> @@ -965,4 +965,33 @@ mcasp2: audio-controller@2b20000 {
> power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
> status = "disabled";
> };
> + gpmc0: memory-controller@3b000000 {
> + compatible = "ti,am64-gpmc";
> + reg = <0x00 0x03b000000 0x00 0x400>,
> + <0x00 0x050000000 0x00 0x8000000>;
> + reg-names = "cfg", "data";
> + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&k3_clks 80 0>;
> + clock-names = "fck";
> + power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
> + gpmc,num-cs = <3>;
> + gpmc,num-waitpins = <2>;
> + #address-cells = <2>;
> + #size-cells = <1>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
As mentioned - document why disabled by default.
> + };
> +
> + elm0: ecc@25010000 {
> + compatible = "ti,am3352-elm";
> + reg = <0x00 0x25010000 0x00 0x2000>;
> + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&k3_clks 54 0>;
> + clock-names = "fck";
> + power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
> + status = "disabled";
As mentioned - document why disabled by default.
> + };
> };
> diff --git a/arch/arm64/boot/dts/ti/k3-am62.dtsi b/arch/arm64/boot/dts/ti/k3-am62.dtsi
> index f1e15206e1ce..b9b1e522d74c 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62.dtsi
> @@ -77,6 +77,8 @@ cbass_main: bus@f0000 {
> <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
> <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
> <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
> + <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0 CFG */
> + <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */
Why not keep it sorted?
>
> /* MCU Domain Range */
> <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
> --
> 2.25.1
>
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
