On Sun, Oct 01, 2023 at 06:34:21AM +0800, Inochi Amaoto wrote:
> Hi, Jisheng
> >Add initial device tree for the CV1800B RISC-V SoC by SOPHGO.
>
> You add the clint dt-bindings of CV1800B clint, but I don't see the clint
> node in this dt. The SBI needs this clint node to provide timer for linux.
> AFAIK, the dt of SBI comes from the linux or the bootloader, and bootloader
> may load the linux dt and pass it to the SBI. I think it is better to add
> the clint node.
> In addition, please separate the peripheral node to a different file, which
> can be reused by both the CV1800 series and CV1810 series.
How do these SoCs differ?
Documentation seems rather lacking, but I was able to find something on
github that suggests there is also a cv180zb. The difference between the
three seems to, from a quick look, be their video encoding capabilities.
Is that correct?
Cheers,
Conor.
> >
> >Signed-off-by: Jisheng Zhang <jszhang@xxxxxxxxxx>
> >---
> > arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 117 ++++++++++++++++++++++++
> > 1 file changed, 117 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> >
> >diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> >new file mode 100644
> >index 000000000000..8829bebaa017
> >--- /dev/null
> >+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> >@@ -0,0 +1,117 @@
> >+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> >+/*
> >+ * Copyright (C) 2023 Jisheng Zhang <jszhang@xxxxxxxxxx>
> >+ */
> >+
> >+#include <dt-bindings/interrupt-controller/irq.h>
> >+
> >+/ {
> >+ compatible = "sophgo,cv1800b";
> >+ #address-cells = <1>;
> >+ #size-cells = <1>;
> >+
> >+ cpus: cpus {
> >+ #address-cells = <1>;
> >+ #size-cells = <0>;
> >+ timebase-frequency = <25000000>;
> >+
> >+ cpu0: cpu@0 {
> >+ compatible = "thead,c906", "riscv";
> >+ device_type = "cpu";
> >+ reg = <0>;
> >+ d-cache-block-size = <64>;
> >+ d-cache-sets = <512>;
> >+ d-cache-size = <65536>;
> >+ i-cache-block-size = <64>;
> >+ i-cache-sets = <128>;
> >+ i-cache-size = <32768>;
> >+ mmu-type = "riscv,sv39";
> >+ riscv,isa = "rv64imafdc";
> >+ riscv,isa-base = "rv64i";
> >+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> >+ "zifencei", "zihpm";
> >+
> >+ cpu0_intc: interrupt-controller {
> >+ compatible = "riscv,cpu-intc";
> >+ interrupt-controller;
> >+ #address-cells = <0>;
> >+ #interrupt-cells = <1>;
> >+ };
> >+ };
> >+ };
> >+
> >+ osc: oscillator {
> >+ compatible = "fixed-clock";
> >+ clock-output-names = "osc_25m";
> >+ #clock-cells = <0>;
> >+ };
> >+
> >+ soc {
> >+ compatible = "simple-bus";
> >+ interrupt-parent = <&plic>;
> >+ #address-cells = <1>;
> >+ #size-cells = <1>;
> >+ dma-noncoherent;
> >+ ranges;
> >+
> >+ uart0: serial@04140000 {
> >+ compatible = "snps,dw-apb-uart";
> >+ reg = <0x04140000 0x100>;
> >+ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
> >+ clocks = <&osc>;
> >+ reg-shift = <2>;
> >+ reg-io-width = <4>;
> >+ status = "disabled";
> >+ };
> >+
> >+ uart1: serial@04150000 {
> >+ compatible = "snps,dw-apb-uart";
> >+ reg = <0x04150000 0x100>;
> >+ interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
> >+ clocks = <&osc>;
> >+ reg-shift = <2>;
> >+ reg-io-width = <4>;
> >+ status = "disabled";
> >+ };
> >+
> >+ uart2: serial@04160000 {
> >+ compatible = "snps,dw-apb-uart";
> >+ reg = <0x04160000 0x100>;
> >+ interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
> >+ clocks = <&osc>;
> >+ reg-shift = <2>;
> >+ reg-io-width = <4>;
> >+ status = "disabled";
> >+ };
> >+
> >+ uart3: serial@04170000 {
> >+ compatible = "snps,dw-apb-uart";
> >+ reg = <0x04170000 0x100>;
> >+ interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
> >+ clocks = <&osc>;
> >+ reg-shift = <2>;
> >+ reg-io-width = <4>;
> >+ status = "disabled";
> >+ };
> >+
> >+ uart4: serial@041c0000 {
> >+ compatible = "snps,dw-apb-uart";
> >+ reg = <0x041c0000 0x100>;
> >+ interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
> >+ clocks = <&osc>;
> >+ reg-shift = <2>;
> >+ reg-io-width = <4>;
> >+ status = "disabled";
> >+ };
> >+
> >+ plic: interrupt-controller@70000000 {
> >+ compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
> >+ reg = <0x70000000 0x4000000>;
> >+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> >+ interrupt-controller;
> >+ #address-cells = <0>;
> >+ #interrupt-cells = <2>;
> >+ riscv,ndev = <101>;
> >+ };
> >+ };
> >+};
> >--
> >2.40.1
> >
> >
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