Add a documentation for the Rockchip Camera Interface controller binding. This controller can be found on platforms such as the PX30 or RK1808, RK3128 and RK3288. The PX30 is the only platform supported so far. Signed-off-by: Mehdi Djait <mehdi.djait@xxxxxxxxxxx> --- .../bindings/media/rockchip-vip.yaml | 91 +++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/rockchip-vip.yaml diff --git a/Documentation/devicetree/bindings/media/rockchip-vip.yaml b/Documentation/devicetree/bindings/media/rockchip-vip.yaml new file mode 100644 index 000000000000..33c603209c39 --- /dev/null +++ b/Documentation/devicetree/bindings/media/rockchip-vip.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/rockchip-vip.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip VIP Camera Interface + +maintainers: + - Mehdi Djait <mehdi.djait@xxxxxxxxxxx> + +description: |- + Rockchip Video Input Processor present on PX30, RK1808, RK3128 and RK3288 + +properties: + compatible: + const: rockchip,px30-vip + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: ACLK + - description: HCLK + - description: PCLK + + clock-names: + items: + - const: aclk + - const: hclk + - const: pclk + + resets: + items: + - description: AXI + - description: AHB + - description: PCLK IN + + reset-names: + items: + - const: axi + - const: ahb + - const: pclkin + + power-domains: + maxItems: 1 + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + description: A connection to a sensor or decoder + +required: + - compatible + - reg + - interrupts + - clocks + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/px30-cru.h> + #include <dt-bindings/power/px30-power.h> + + parent0: parent { + #address-cells = <2>; + #size-cells = <2>; + + vip: vip@ff490000 { + compatible = "rockchip,px30-vip"; + reg = <0x0 0xff490000 0x0 0x200>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>; + clock-names = "aclk", "hclk", "pclk"; + resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>; + reset-names = "axi", "ahb", "pclkin"; + power-domains = <&power PX30_PD_VI>; + port { + vip_in: endpoint { + remote-endpoint = <&tw9900_out>; + }; + }; + }; + }; +... -- 2.41.0
