Add USB Super-Speed UNIPHY node and populate the phandle on gcc node for the parent clock map. Signed-off-by: Praveenkumar I <quic_ipkumar@xxxxxxxxxxx> --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index d3fef2f80a81..b08ffd8c094e 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -158,6 +158,29 @@ usbphy0: phy@7b000 { status = "disabled"; }; + usbphy1: phy@4b0000 { + compatible = "qcom,ipq5332-usb-uniphy"; + reg = <0x4b0000 0x800>; + + clocks = <&gcc GCC_PCIE3X1_PHY_AHB_CLK>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB0_PIPE_CLK>; + clock-names = "ahb", + "cfg_ahb", + "pipe"; + + resets = <&gcc GCC_USB0_PHY_BCR>; + + #clock-cells = <0>; + clock-output-names = "usb0_pipe_clk_src"; + + qcom,phy-usb-mux-sel = <&tcsr 0x10540>; + + #phy-cells = <0>; + + status = "disabled"; + }; + qfprom: efuse@a4000 { compatible = "qcom,ipq5332-qfprom", "qcom,qfprom"; reg = <0x000a4000 0x721>; @@ -200,7 +223,7 @@ gcc: clock-controller@1800000 { <&sleep_clk>, <0>, <0>, - <0>; + <&usbphy1>; }; tcsr_mutex: hwlock@1905000 { -- 2.34.1