On Fri, 2023-09-22 at 10:29 +0200, AngeloGioacchino Del Regno wrote:
> Il 22/09/23 08:50, Moudy Ho ha scritto:
> > Add device nodes for Media Data Path 3 (MDP3) modules.
> >
> > Signed-off-by: Moudy Ho <moudy.ho@xxxxxxxxxxxx>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 388
> > +++++++++++++++++++++++
> > 1 file changed, 388 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > index 4dbbf8fdab75..cf61ba7b8956 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > @@ -1960,6 +1960,114 @@
> > #clock-cells = <1>;
> > };
> >
>
> ..snip..
>
> > +
> > + display@14006000 {
> > + compatible = "mediatek,mt8183-mdp3-rsz";
>
> Please always add a SoC-specific compatible (both here and in
> bindings).
>
> compatible = "medaitek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
>
> > + reg = <0 0x14006000 0 0x1000>;
> > + mediatek,gce-client-reg = <&gce1
> > SUBSYS_1400XXXX 0x6000 0x1000>;
> > + mediatek,gce-events =
> > <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>,
> > + <CMDQ_EVENT_VPP0_MDP_RSZ_
> > FRAME_DONE>;
> > + clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>;
> > + };
> > +
>
> ..snip..
>
> > +
> > + dma-controller@1400c000 {
> > + compatible = "mediatek,mt8183-mdp3-wrot";
>
> same here
>
> > + reg = <0 0x1400c000 0 0x1000>;
> > + mediatek,gce-client-reg = <&gce1
> > SUBSYS_1400XXXX 0xc000 0x1000>;
> > + mediatek,gce-events =
> > <CMDQ_EVENT_VPP0_MDP_WROT_SOF>,
> > + <CMDQ_EVENT_VPP0_MDP_WROT
> > _VIDO_WDONE>;
> > + clocks = <&vppsys0 CLK_VPP0_MDP_WROT>;
> > + iommus = <&iommu_vpp M4U_PORT_L4_MDP_WROT>;
> > + power-domains = <&spm
> > MT8195_POWER_DOMAIN_VPPSYS0>;
> > + #dma-cells = <1>;
> > + };
> > +
> > mutex@1400f000 {
> > compatible = "mediatek,mt8195-vpp-mutex";
> > reg = <0 0x1400f000 0 0x1000>;
> > @@ -2107,6 +2215,286 @@
> > power-domains = <&spm
> > MT8195_POWER_DOMAIN_VPPSYS1>;
> > };
> >
>
> ..snip..
>
> > +
> > + display@14f14000 {
> > + compatible = "mediatek,mt8183-mdp3-rsz";
>
> and here
>
> > + reg = <0 0x14f14000 0 0x1000>;
> > + mediatek,gce-client-reg = <&gce1
> > SUBSYS_14f1XXXX 0x4000 0x1000>;
> > + mediatek,gce-events =
> > <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF>,
> > + <CMDQ_EVENT_VPP1_SVPP1_MD
> > P_RSZ_FRAME_DONE>;
> > + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>;
> > + };
> > +
> > + display@14f15000 {
> > + compatible = "mediatek,mt8183-mdp3-rsz";
>
> ...and here
>
> > + reg = <0 0x14f15000 0 0x1000>;
> > + mediatek,gce-client-reg = <&gce1
> > SUBSYS_14f1XXXX 0x5000 0x1000>;
> > + mediatek,gce-events =
> > <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>,
> > + <CMDQ_EVENT_VPP1_SVPP2_MD
> > P_RSZ_FRAME_DONE>;
> > + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>;
> > + };
> > +
> > + display@14f16000 {
> > + compatible = "mediatek,mt8183-mdp3-rsz";
>
> ......and here.
>
> > + reg = <0 0x14f16000 0 0x1000>;
> > + mediatek,gce-client-reg = <&gce1
> > SUBSYS_14f1XXXX 0x6000 0x1000>;
> > + mediatek,gce-events =
> > <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>,
> > + <CMDQ_EVENT_VPP1_SVPP3_MD
> > P_RSZ_FRAME_DONE>;
> > + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>;
> > + };
> > +
>
> ..snip..
>
> > +
> > + dma-controller@14f23000 {
> > + compatible = "mediatek,mt8183-mdp3-wrot";
>
> ...again... and for the other two occurrences of wrot as well.
>
> Apart from that, looks good.
>
> Regards,
> Angelo
>
Hi Angelo,
Thank you for the advice, I will include the appropriate compatible
names to the specified locations.
Sincerely,
Moudy
> > + reg = <0 0x14f23000 0 0x1000>;
> > + mediatek,gce-client-reg = <&gce1
> > SUBSYS_14f2XXXX 0x3000 0x1000>;
> > + mediatek,gce-events =
> > <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF>,
> > + <CMDQ_EVENT_VPP1_SVPP1_MD
> > P_WROT_FRAME_DONE>;
> > + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>;
> > + iommus = <&iommu_vdo
> > M4U_PORT_L5_SVPP1_MDP_WROT>;
> > + power-domains = <&spm
> > MT8195_POWER_DOMAIN_VPPSYS1>;
> > + #dma-cells = <1>;
> > + };
> > +
> > + dma-controller@14f24000 {
> > + compatible = "mediatek,mt8183-mdp3-wrot";
> > + reg = <0 0x14f24000 0 0x1000>;
> > + mediatek,gce-client-reg = <&gce1
> > SUBSYS_14f2XXXX 0x4000 0x1000>;
> > + mediatek,gce-events =
> > <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>,
> > + <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT
> > _FRAME_DONE>;
> > + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>;
> > + iommus = <&iommu_vdo
> > M4U_PORT_L5_SVPP2_MDP_WROT>;
> > + power-domains = <&spm
> > MT8195_POWER_DOMAIN_VPPSYS1>;
> > + #dma-cells = <1>;
> > + };
> > +
> > + dma-controller@14f25000 {
> > + compatible = "mediatek,mt8183-mdp3-wrot";
> > + reg = <0 0x14f25000 0 0x1000>;
> > + mediatek,gce-client-reg = <&gce1
> > SUBSYS_14f2XXXX 0x5000 0x1000>;
> > + mediatek,gce-events =
> > <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>,
> > + <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT
> > _FRAME_DONE>;
> > + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>;
> > + iommus = <&iommu_vpp
> > M4U_PORT_L6_SVPP3_MDP_WROT>;
> > + power-domains = <&spm
> > MT8195_POWER_DOMAIN_VPPSYS1>;
> > + #dma-cells = <1>;
> > + };
> > +
> > imgsys: clock-controller@15000000 {
> > compatible = "mediatek,mt8195-imgsys";
> > reg = <0 0x15000000 0 0x1000>;
>
>
