On Sun, 24 Sept 2023 at 21:31, Krzysztof Kozlowski
<krzysztof.kozlowski@xxxxxxxxxx> wrote:
>
> The SDX65 GCC clock controller expects two required clocks:
> pcie_pipe_clk and usb3_phy_wrapper_gcc_usb30_pipe_clk. The first one is
> provided by existing phy node, but second is not yet implemented.
>
> qcom-sdx65-mtp.dtb: clock-controller@100000: clocks: [[11, 0], [11, 1], [12]] is too short
> qcom-sdx65-mtp.dtb: clock-controller@100000: clock-names: ['bi_tcxo', 'bi_tcxo_ao', 'sleep_clk'] is too short
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
> ---
> arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
> index c9790217320b..4a8cc28fa1db 100644
> --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
> +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
> @@ -204,8 +204,16 @@ soc: soc {
> gcc: clock-controller@100000 {
> compatible = "qcom,gcc-sdx65";
> reg = <0x00100000 0x001f7400>;
> - clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>;
> - clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&rpmhcc RPMH_CXO_CLK_A>,
> + <&sleep_clk>,
> + <&pcie_phy>,
> + <0>;
Maybe <&usb_ssphy> or <&usb_qmpphy>?
> + clock-names = "bi_tcxo",
> + "bi_tcxo_ao",
> + "sleep_clk",
> + "pcie_pipe_clk",
> + "usb3_phy_wrapper_gcc_usb30_pipe_clk";
> #power-domain-cells = <1>;
> #clock-cells = <1>;
> #reset-cells = <1>;
> --
> 2.34.1
>
--
With best wishes
Dmitry
