On Sat, Sep 23, 2023 at 03:50:36PM +0800, Guo Ren wrote:
> On Fri, Sep 22, 2023 at 4:16 PM Conor Dooley <conor@xxxxxxxxxx> wrote:
> >
> > From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> >
> > Convert the th1520 devicetrees to use the new properties
> > "riscv,isa-base" & "riscv,isa-extensions".
> > For compatibility with other projects, "riscv,isa" remains.
> >
> > Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> > ---
> > arch/riscv/boot/dts/thead/th1520.dtsi | 12 ++++++++++++
> > 1 file changed, 12 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> > index ce708183b6f6..723f65487246 100644
> > --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> > +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> > @@ -20,6 +20,9 @@ c910_0: cpu@0 {
> > compatible = "thead,c910", "riscv";
> > device_type = "cpu";
> > riscv,isa = "rv64imafdc";
> > + riscv,isa-base = "rv64i";
> Why not riscv,isa-base = "rv64"? I saw "i" in the riscv,isa-extensions.
I did it that way as a hedge against things changing in the future. I
have little trust in that part of the ISA specifications.
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