On Wed, Sep 20, 2023 at 03:09:54PM +0200, Alvin Šipraga wrote: > From: Alvin Šipraga <alsi@xxxxxxxxxxxxxxx> > > For applications where the PLL must be adjusted without glitches in the > clock output(s), a new silabs,pll-reset-mode property is added. It > can be used to specify whether or not the PLL should be reset after > adjustment. Resetting is known to cause glitches. > > For compatibility with older device trees, it must be assumed that the > default PLL reset mode is to unconditionally reset after adjustment. > > Cc: Sebastian Hesselbarth <sebastian.hesselbarth@xxxxxxxxx> > Cc: Rabeeh Khoury <rabeeh@xxxxxxxxxxxxx> > Cc: Jacob Siverskog <jacob@teenage.engineering> > Cc: Sergej Sawazki <sergej@xxxxxxxxxx> > Signed-off-by: Alvin Šipraga <alsi@xxxxxxxxxxxxxxx> > --- > .../bindings/clock/silabs,si5351.yaml | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.yaml b/Documentation/devicetree/bindings/clock/silabs,si5351.yaml > index 3ca8d998c48c..b6692b323a66 100644 > --- a/Documentation/devicetree/bindings/clock/silabs,si5351.yaml > +++ b/Documentation/devicetree/bindings/clock/silabs,si5351.yaml > @@ -50,6 +50,22 @@ properties: > Pair of <number source> for each PLL. Allows to overwrite clock source of > PLL A (number=0) or PLL B (number=1). > > + silabs,pll-reset-mode: > + $ref: /schemas/types.yaml#/definitions/uint32-matrix > + minItems: 1 > + maxItems: 2 > + description: | > + Pair of <number mode> for each PLL. Configures the reset mode for PLL A > + (number=0) and/or PLL B (number=1). Mode can be one of: > + > + 0 - reset whenever PLL rate is adjusted (default mode) > + 1 - do not reset when PLL rate is adjusted > + > + In mode 1, the PLL is only reset if the silabs,pll-reset is specified in > + one of the clock output child nodes that also sources the PLL. This mode > + may be preferable if output clocks are expected to be adjusted without > + glitches. Same comments as the other matrix property. > + > patternProperties: > "^clkout@?[0-8]$": > type: object > @@ -205,6 +221,9 @@ examples: > /* Use XTAL input as source of PLL0 and PLL1 */ > silabs,pll-source = <0 0>, <1 0>; > > + /* Don't reset PLL1 on rate adjustment */ > + silabs,pll-reset-mode = <1 1>; > + > /* > * Overwrite CLK0 configuration with: > * - 8 mA output drive strength > -- > 2.41.0 >
