On Mon, Sep 18, 2023 at 11:26:34PM +0100, Daniel Golle wrote: > Add several phandles needed for Ethernet SerDes interfaces on the > MediaTek MT7988 SoC. > > Signed-off-by: Daniel Golle <daniel@xxxxxxxxxxxxxx> > --- > .../devicetree/bindings/net/mediatek,net.yaml | 28 +++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml > index e74502a0afe86..78219158b96af 100644 > --- a/Documentation/devicetree/bindings/net/mediatek,net.yaml > +++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml > @@ -385,6 +385,34 @@ allOf: > minItems: 2 > maxItems: 2 > > + mediatek,toprgu: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + Phandle to the syscon representing the reset controller. Use the reset binding > + > + mediatek,usxgmiisys: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + minItems: 2 > + maxItems: 2 > + items: > + maxItems: 1 > + description: > + A list of phandle to the syscon node referencing the USXGMII PCS. Use the PCS binding > + > + mediatek,xfi-pextp: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + minItems: 2 > + maxItems: 2 > + items: > + maxItems: 1 > + description: > + A list of phandle to the syscon node that handles the 10GE SerDes PHY. Use the phy binding (phys, not phy-handle for ethernet PHY). > + > + mediatek,xfi-pll: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + Phandle to the syscon node handling the 10GE SerDes clock setup. Use the clock binding > + > patternProperties: > "^mac@[0-1]$": > type: object > -- > 2.42.0
