On Mon, Sep 18, 2023 at 07:59:16PM +0200, Benjamin Bara wrote: > Hi Adam! > > On Mon, 18 Sept 2023 at 07:00, Adam Ford <aford173@xxxxxxxxx> wrote: > > On Sun, Sep 17, 2023 at 3:40 PM Benjamin Bara <bbara93@xxxxxxxxx> wrote: > > > The idea: > > > Enable CLK_SET_RATE_PARENT, at least for media_disp2_pix and media_ldb. > > > When this is done, ensure that the pll1443x can be re-configured, > > > meaning it ensures that an already configured rate (crtc rate) is still > > > supported when a second child requires a different rate (lvds rate). As > > > > Have you tested with the DSI as well? If memory servers, the DSI > > clock and the LVDS clock are both clocked from the same video_pll. At > > one time, I had done some experimentation with trying the DSI > > connected to an HDMI bridge chip connected to a monitor and the LVDS > > was connected to a display panel with a static resolution and refresh > > rate. For my LVDS display, it needs 30MHz to display properly, but > > various HDMI resolutions needed values that were not evenly divisible > > by 30MHz which appeared to cause display sync issues when trying to > > share a clock that was trying to dynamically adjust for two different > > displays especially when trying to change the resoltuion of the HDMI > > display to various values for different resolutions. > > Unfortunately I haven't. I think if you have the use case to support > different "run-time-dynamic" (HDMI) rates in parallel with a static > (LVDS) rate If anything, LVDS is harder to deal with than HDMI. HDMI only has a handful of clock rates (74.250, 148.5, 297 and 594MHz mostly) while LVDS is more freeform. We are more likely to change the rate on an HDMI device though, but a rate change from 1080p to 720p would only require a divide by two (from 148.5 to 74.250) so fairly easy to do. Maxime
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