Hi, Shuijing: On Tue, 2023-08-22 at 10:41 +0800, Shuijing Li wrote: > Add support MT8188 dp/edp function Reviewed-by: CK Hu <ck.hu@xxxxxxxxxxxx> > > Signed-off-by: Shuijing Li <shuijing.li@xxxxxxxxxxxx> > --- > Changes in v6: > Move audio function to patch [2/4]. > per suggestion from the previous thread: > https://lore.kernel.org/all/1d41747060c613ca0ae8e3b6395cc33bfa4d9056.camel@xxxxxxxxxxxx/ > Changes in v5: > Separate mt8188 related code into mtk_dp_data structure and mt8188 > dp/edp function > per suggestion from the previous thread: > https://lore.kernel.org/lkml/c1c84616f3da83a8a2bc245b0d3c7697153cd81a.camel@xxxxxxxxxxxx/ > --- > drivers/gpu/drm/mediatek/mtk_dp.c | 17 +++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_dp_reg.h | 6 ++++++ > 2 files changed, 23 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c > b/drivers/gpu/drm/mediatek/mtk_dp.c > index 0ba9a4fdf839..67986dd7c9d7 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dp.c > +++ b/drivers/gpu/drm/mediatek/mtk_dp.c > @@ -2631,6 +2631,15 @@ static int mtk_dp_resume(struct device *dev) > > static SIMPLE_DEV_PM_OPS(mtk_dp_pm_ops, mtk_dp_suspend, > mtk_dp_resume); > > +static const struct mtk_dp_data mt8188_dp_data = { > + .bridge_type = DRM_MODE_CONNECTOR_DisplayPort, > + .smc_cmd = MTK_DP_SIP_ATF_VIDEO_UNMUTE, > + .efuse_fmt = mt8195_dp_efuse_fmt, > + .audio_supported = true, > + .audio_pkt_in_hblank_area = true, > + .audio_m_div2_bit = > MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2, > +}; > + > static const struct mtk_dp_data mt8195_edp_data = { > .bridge_type = DRM_MODE_CONNECTOR_eDP, > .smc_cmd = MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE, > @@ -2648,6 +2657,14 @@ static const struct mtk_dp_data mt8195_dp_data > = { > }; > > static const struct of_device_id mtk_dp_of_match[] = { > + { > + .compatible = "mediatek,mt8188-edp-tx", > + .data = &mt8195_edp_data, > + }, > + { > + .compatible = "mediatek,mt8188-dp-tx", > + .data = &mt8188_dp_data, > + }, > { > .compatible = "mediatek,mt8195-edp-tx", > .data = &mt8195_edp_data, > diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h > b/drivers/gpu/drm/mediatek/mtk_dp_reg.h > index b9859ef067ce..709b79480693 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h > +++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h > @@ -165,6 +165,12 @@ > #define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2 (5 << > 8) > #define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_4 (6 << > 8) > #define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_8 (7 << > 8) > +#define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2 (1 << > 8) > +#define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_4 (2 << > 8) > +#define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_8 (3 << > 8) > +#define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2 (4 << > 8) > +#define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_4 (5 << > 8) > +#define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_8 (7 << > 8) > #define MTK_DP_ENC0_P0_30D8 0x30d8 > #define MTK_DP_ENC0_P0_312C 0x312c > #define ASP_HB2_DP_ENC0_P0_MASK GENMASK > (7, 0)
