From: Benjamin Bara <benjamin.bara@xxxxxxxxxxx>
Similar to commit 07bb2e368820 ("arm64: dts: imx8mp: Fix video clock
parents") the parent of IMX8MP_CLK_MEDIA_MIPI_PHY1_REF should be set in
the media_blk_ctrl. Currently, if mipi_dsi is not in use, its parent is
set to IMX8MP_VIDEO_PLL1_OUT, and might therefore clash with the
constraints coming from a panel.
Cc: Adam Ford <aford173@xxxxxxxxx>
Signed-off-by: Benjamin Bara <benjamin.bara@xxxxxxxxxxx>
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index c946749a3d73..9539d747e28e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1640,11 +1640,6 @@ mipi_dsi: dsi@32e60000 {
clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
clock-names = "bus_clk", "sclk_mipi";
- assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>,
- <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
- assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
- <&clk IMX8MP_CLK_24M>;
- assigned-clock-rates = <200000000>, <24000000>;
samsung,pll-clock-frequency = <24000000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>;
@@ -1747,13 +1742,16 @@ media_blk_ctrl: blk-ctrl@32ec0000 {
<&clk IMX8MP_CLK_MEDIA_APB>,
<&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
<&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
- <&clk IMX8MP_VIDEO_PLL1>;
+ <&clk IMX8MP_VIDEO_PLL1>,
+ <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_VIDEO_PLL1_OUT>,
- <&clk IMX8MP_VIDEO_PLL1_OUT>;
+ <&clk IMX8MP_VIDEO_PLL1_OUT>,
+ <&clk IMX8MP_CLK_24M>;
assigned-clock-rates = <500000000>, <200000000>,
- <0>, <0>, <1039500000>;
+ <0>, <0>, <1039500000>,
+ <24000000>;
#power-domain-cells = <1>;
lvds_bridge: bridge@5c {
--
2.34.1
