Add dts node for socinfo retrieval for the following projects:
MT8173, MT8183, MT8186, MT8192, MT8195
Signed-off-by: William-tw Lin <william-tw.lin@xxxxxxxxxxxx>
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 15 +++++++++++++++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 15 +++++++++++++++
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 10 ++++++++++
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 14 ++++++++++++++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 9 +++++++++
5 files changed, 63 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index c47d7d900f28..8cac18ed7833 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -590,6 +590,15 @@
reg = <0 0x10206000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+
+ socinfo_data1: socinfo-data1 {
+ reg = <0x040 0x4>;
+ };
+
+ socinfo_data2: socinfo-data2 {
+ reg = <0x044 0x4>;
+ };
+
thermal_calibration: calib@528 {
reg = <0x528 0xc>;
};
@@ -1520,4 +1529,10 @@
power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>;
};
};
+
+ socinfo {
+ compatible = "mediatek,socinfo";
+ nvmem-cells = <&socinfo_data1 &socinfo_data2>;
+ nvmem-cell-names = "socinfo-data1", "socinfo-data2";
+ };
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 5169779d01df..b17af0edb198 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1706,6 +1706,15 @@
reg = <0 0x11f10000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+
+ socinfo_data1: socinfo-data1 {
+ reg = <0x04C 0x4>;
+ };
+
+ socinfo_data2: socinfo-data2 {
+ reg = <0x060 0x4>;
+ };
+
thermal_calibration: calib@180 {
reg = <0x180 0xc>;
};
@@ -2105,4 +2114,10 @@
power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
};
};
+
+ socinfo {
+ compatible = "mediatek,socinfo";
+ nvmem-cells = <&socinfo_data1 &socinfo_data2>;
+ nvmem-cell-names = "socinfo-data1", "socinfo-data2";
+ };
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index f04ae70c470a..860559d239a0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -1660,6 +1660,10 @@
reg = <0x59c 0x4>;
bits = <0 3>;
};
+
+ socinfo_data1: socinfo-data1 {
+ reg = <0x7a0 0x4>;
+ };
};
mipi_tx0: dsi-phy@11cc0000 {
@@ -2083,4 +2087,10 @@
power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;
};
};
+
+ socinfo {
+ compatible = "mediatek,socinfo";
+ nvmem-cells = <&socinfo_data1>;
+ nvmem-cell-names = "socinfo-data1";
+ };
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 5e94cb4aeb44..3e1315da3b56 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1122,6 +1122,14 @@
#address-cells = <1>;
#size-cells = <1>;
+ socinfo_data1: socinfo-data1 {
+ reg = <0x044 0x4>;
+ };
+
+ socinfo_data2: socinfo-data2 {
+ reg = <0x050 0x4>;
+ };
+
lvts_e_data1: data1@1c0 {
reg = <0x1c0 0x58>;
};
@@ -1901,4 +1909,10 @@
power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
};
};
+
+ socinfo {
+ compatible = "mediatek,socinfo";
+ nvmem-cells = <&socinfo_data1 &socinfo_data2>;
+ nvmem-cell-names = "socinfo-data1", "socinfo-data2";
+ };
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 48b72b3645e1..17c4805d7963 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1683,6 +1683,9 @@
lvts_efuse_data2: lvts2-calib@1d0 {
reg = <0x1d0 0x38>;
};
+ socinfo_data1: socinfo-data1 {
+ reg = <0x7a0 0x4>;
+ };
};
u3phy2: t-phy@11c40000 {
@@ -3519,4 +3522,10 @@
};
};
};
+
+ socinfo {
+ compatible = "mediatek,socinfo";
+ nvmem-cells = <&socinfo_data1>;
+ nvmem-cell-names = "socinfo-data1";
+ };
};
--
2.18.0
