On 14/09/2023 16:56, Laurentiu Tudor wrote:
> Wrap the usb controllers in an intermediate simple-bus and use it to
> constrain the dma address size of these usb controllers to the 40b
> that they generate toward the interconnect. This is required because
> the SoC uses 48b address sizes and this mismatch would lead to smmu
> context faults [1] because the usb generates 40b addresses while the
> smmu page tables are populated with 48b wide addresses.
>
> [1]
> xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
> xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
> xhci-hcd xhci-hcd.0.auto: hcc params 0x0220f66d hci version 0x100 quirks 0x0000000002000010
> xhci-hcd xhci-hcd.0.auto: irq 108, io mem 0x03100000
> xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
> xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
> xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
> arm-smmu 5000000.iommu: Unhandled context fault: fsr=0x402, iova=0xffffffb000, fsynr=0x0, cbfrsynra=0xc01, cb=3
>
> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@xxxxxxx>
> ---
> .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 46 +++++++++++--------
> 1 file changed, 27 insertions(+), 19 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
> index d2f5345d0560..47cc7699ca16 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
> @@ -1186,26 +1186,34 @@
> dma-coherent;
> };
>
> - usb0: usb@3100000 {
> - status = "disabled";
> - compatible = "snps,dwc3";
> - reg = <0x0 0x3100000 0x0 0x10000>;
> - interrupts = <0 80 0x4>; /* Level high type */
> - dr_mode = "host";
> - snps,quirk-frame-length-adjustment = <0x20>;
> - snps,dis_rxdet_inp3_quirk;
> - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
> - };
> + aux_bus: aux_bus {
No underscores in node names. The node name should be anyway generic, so
just "bus".
Best regards,
Krzysztof
