On 14/09/2023 07:46, Luo Jie wrote: > The clock controller driver of qca8386/qca8084 is registered > as the MDIO device, the hardware register is accessed by MDIO bus > that is normally used to access general PHY device, which is > different from the current existed qcom clock controller drivers > using ioremap to access hardware clock registers. > > MDIO bus is common utilized by both qca8386/qca8084 and other > PHY devices, so the mutex lock mdio_bus->mdio_lock should be > used instead of using the mutex lock of remap. > > To access the hardware clock registers of qca8386/qca8084, there > is special MDIO frame sequence(three MDIO read/write operations) > need to be sent to device. > > Signed-off-by: Luo Jie <quic_luoj@xxxxxxxxxxx> > --- > drivers/clk/qcom/Kconfig | 9 + > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/nsscc-qca8k.c | 2178 ++++++++++++++++++++++++++++++++ > 3 files changed, 2188 insertions(+) > create mode 100644 drivers/clk/qcom/nsscc-qca8k.c > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index 865db5202e4c..c95ada6a1385 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -203,6 +203,15 @@ config IPQ_GCC_9574 > i2c, USB, SD/eMMC, etc. Select this for the root clock > of ipq9574. > > +config IPQ_NSSCC_QCA8K > + tristate "QCA8K(QCA8386 or QCA8084) NSS Clock Controller" > + depends on MDIO_BUS || COMPILE_TEST This is SoC is for both ARM and ARM64 worlds? > + help > + Support for NSS(Network SubSystem) clock controller on > + qca8386/qca8084 chip. > + Say Y or M if you want to use network features of switch or > + PHY device. Select this for the root clock of qca8k. > + Best regards, Krzysztof
