On Tue, Sep 12, 2023 at 05:27:31PM +0100, Conor Dooley wrote:
> On Tue, Sep 12, 2023 at 03:22:32PM +0800, Jisheng Zhang wrote:
> > riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't
> > dma coherent, so set dma-noncoherent to reflect this fact.
> >
> > Signed-off-by: Jisheng Zhang <jszhang@xxxxxxxxxx>
> > Tested-by: Drew Fustini <dfustini@xxxxxxxxxxxx>
> > ---
> >
> > Since v1:
> > - rebase on v6.6-rc1
> > - collect Tested-by tag
>
> Does this mean you're expecting me to take this?
Hi Conor,
I think I will take this and send PR to soc people. The reason
I send v2 is the rebasing on new rc1 and v1 wasn't in linux-riscv
mailist due to typo;
Thank you so much
>
> >
> > arch/riscv/boot/dts/thead/th1520.dtsi | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> > index ce708183b6f6..ff364709a6df 100644
> > --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> > +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> > @@ -139,6 +139,7 @@ soc {
> > interrupt-parent = <&plic>;
> > #address-cells = <2>;
> > #size-cells = <2>;
> > + dma-noncoherent;
> > ranges;
> >
> > plic: interrupt-controller@ffd8000000 {
> > --
> > 2.40.1
> >
