在 2023/9/4 8:57, Bryan O'Donoghue 写道:
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I've checked the documentation for this chip.
gpio20, gpio21 = blsp0_uart0
gpio28, gpio29 = blsp0_uart0
These pins are muxed to UART0, I agree, the u-boot dts also indicates
this also.
If we open the documentation further we see
0x78AF000 = BLSP1_BLSP_UART0
0x79b0000 = BLSP1_BLSP_UART1
So for starters the dtsi has the _wrong_ label.
Here/anseo
grep uart0: arch/arm64/boot/dts/qcom/*
arch/arm64/boot/dts/qcom/ipq5332.dtsi: blsp1_uart0: serial@78af000 {
arch/arm64/boot/dts/qcom/ipq9574.dtsi: blsp1_uart0: serial@78af000 {
That's how that label ought to be the main hint something is askance is
assigning a pin named "blsp0_uart0" to a dts entry named "blsp1_uart1".
Please update the label in your next revision.
---
bod
I think the root cause is the confused name in pinctrl. I will update
the mux index to alphabetical order in next patch.
By the way, can you find out the documents about the pinmux map. For
example, the code of pinctrl only show that GPIO20,21 are for UART0. But
which pin is TX and which is RX? And yes, because of UART, it's easy to
find out.
But what I want to known is "blsp2_spi". It has 3 pinmux configs -
"blsp2_spi" (GPIO27), "blsp2_spi0" (GPIO31,32,33,34) and "blsp2_spi1"
(GPIO23,24,25,26). What "blsp2_spi" (GPIO27) for?
