> Sure Rob, I will change the description to below.
>
> description:
> Indicates that the PHY output pin (COL) is routed to ICSSG GPIO
The PHY has multiple output pins, so i would not put COL in brackets,
but make it explicit which pin you are referring to.
> pin (PRGx_PRU0/1_GPIO10) as input and ICSSG MII port is capable
> of half duplex operations.
"input and so the ICSSG MII port is"
Andrew
