Il 09/09/23 15:28, Macpaul Lin ha scritto:
Add basic device-tree for the Genio 1200-EVK board. This board is made by MediaTek and has a MT8395 SoC (MT8195 family), associated with the MT6359 and MT6360 PMICs, and the MT7921 connectivity chip. The IOs available on that board are: * 1 USB Type-C connector with DP aux mode support * 2 USB Type-A connector with a USB hub * 1 micro-USB port for gadget or OTG support * 1 full size HDMI RX and 1 full size HDMI TX connector * 1 micro SD slot * 40 pins header * SPI interface header * 1 M.2 slot * 1 audio jack * 1 micro-USB port for serial debug * 2 connectors for DSI displays, 1 of the DSI panel is installed * 3 connectors for CSI cameras * 1 connector for a eDP panel * 1 MMC storage * 1 Touch Panel (installed DSI display) * 1 M.2 slot for 5G dongle This commit adds basic support in order to be able to boot. Signed-off-by: Ben Lok <ben.lok@xxxxxxxxxxxx> Signed-off-by: Macpaul Lin <macpaul.lin@xxxxxxxxxxxx> --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../dts/mediatek/mt8395-genio-1200-evk.dts | 901 ++++++++++++++++++ 2 files changed, 902 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts Changes for v2: - correct SOC binding to "mediatek,mt8395". - Fix a Linux coding style comments for optee node. - Fix wifi fixed 3.3v power's node with "wifi-3v3-regulator". - Fix node name of mt6360 and mt6517 to generic dts name as "pmic". - Remove unecessary blank line. - Reording usb node as the order of "phy" then "host". Changes for v3: - Add back bindings for "mediatek,mt8195". - Fix wifi fixed 3.3v power's node with "regulator-2" Changes for v4: - Fix Makefile and dts file name with prefix "mt8395-". - Re-order all nodes in mt8395-genio-1200-evk.dts by alphabetical order. - Remove unused "DEBUG" node. Changes for v5: - Revise commit message for board's name. - swap the order of nodes 'mt6359_vcamio_ldo_reg' and 'mt6359_vcn33_2_bt_ldo_reg' by alphabetical order. - Reorder some gpio pins by alphabetical order. - audio_default_pins, eth pins, and uart1 pins diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index c99c3372a4b5..10e640c6ae08 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -53,4 +53,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts new file mode 100644 index 000000000000..5de2d102c577 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts @@ -0,0 +1,901 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Ben Lok <ben.lok@xxxxxxxxxxxx> + * Macpaul Lin <macpaul.lin@xxxxxxxxxxxx> + */ +/dts-v1/; + +#include "mt8195.dtsi" +#include "mt6359.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/mt8195-pinfunc.h> +#include <dt-bindings/regulator/mediatek,mt6360-regulator.h> +#include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/usb/pd.h> + +/ { + model = "MediaTek Genio 1200 EVK-P1V2-EMMC"; + compatible = "mediatek,mt8395-evk", "mediatek,mt8395", + "mediatek,mt8195"; +
..snip..
+&spi1 { + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + mediatek,pad-select = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + cs-gpios = <&pio 64 GPIO_ACTIVE_LOW>; + + can0: can@0 { + compatible = "microchip,mcp2518fd"; + reg = <0>; + clocks = <&can_clk>; + spi-max-frequency = <20000000>; + interrupts-extended = <&pio 16 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&mt6359_vcn33_2_bt_ldo_reg>; + xceiver-supply = <&mt6359_vcn33_2_bt_ldo_reg>; + }; +}; + +&spi2 { + pinctrl-0 = <&spi2_pins>; + pinctrl-names = "default"; + mediatek,pad-select = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + +&u3phy0 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +}; + +&u3phy3 { + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&ufsphy { + status = "disabled"; +}; + +&spmi {
spmi goes before u3phy0, after spi2. after fixing: Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>
+ #address-cells = <2>; + #size-cells = <0>; + + mt6315_6: pmic@6 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x6 SPMI_USID>; + + regulators { + mt6315_6_vbuck1: vbuck1 { + regulator-compatible = "vbuck1"; + regulator-name = "Vbcpu"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + }; + }; + + mt6315_7: pmic@7 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x7 SPMI_USID>; + + regulators { + mt6315_7_vbuck1: vbuck1 { + regulator-compatible = "vbuck1"; + regulator-name = "Vgpu"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + }; + }; + }; +}; + +&xhci0 { + status = "okay"; +}; + +&xhci1 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&xhci2 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&xhci3 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +};