There is a SoC between dwc and DMA block (ie. PL330)
that does not have a burst signal and supports only single.
So write not-support-burst property on dts, it support single DMA mode.
Signed-off-by: Myunguk Kim <mwkim@xxxxxxxxxxxxx>
---
.../bindings/sound/snps,designware-i2s.yaml | 3 +++
include/sound/designware_i2s.h | 1 +
sound/soc/dwc/dwc-i2s.c | 12 ++++++++++--
3 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml b/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
index a48d040b0a4f..43a46ba2a70c 100644
--- a/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
+++ b/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
@@ -86,6 +86,9 @@ properties:
The phandle to System Register Controller syscon node and the I2S-rx(ADC)
enabled control offset and mask of SYS_SYSCONSAIF__SYSCFG register.
+ no-burst:
+ description: Use single transaction only between DesignWare I2S and DMA IP.
+
allOf:
- $ref: dai-common.yaml#
- if:
diff --git a/include/sound/designware_i2s.h b/include/sound/designware_i2s.h
index f6803205a9fb..f0207f21f09d 100644
--- a/include/sound/designware_i2s.h
+++ b/include/sound/designware_i2s.h
@@ -36,6 +36,7 @@ struct i2s_platform_data
{ #define DW_I2S_QUIRK_COMP_REG_OFFSET (1 << 0)
#define DW_I2S_QUIRK_COMP_PARAM1 (1 << 1)
#define DW_I2S_QUIRK_16BIT_IDX_OVERRIDE (1 << 2)
+ #define DW_I2S_QUIRK_NO_BURST (1 << 3)
unsigned int quirks;
unsigned int i2s_reg_comp1;
unsigned int i2s_reg_comp2;
diff --git a/sound/soc/dwc/dwc-i2s.c b/sound/soc/dwc/dwc-i2s.c
index 5ab1b3eb2d28..71ff894035a4 100644
--- a/sound/soc/dwc/dwc-i2s.c
+++ b/sound/soc/dwc/dwc-i2s.c
@@ -713,7 +713,10 @@ static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev,
dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;
dev->play_dma_data.dt.fifo_size = fifo_depth *
(fifo_width[idx2]) >> 8;
- dev->play_dma_data.dt.maxburst = 16;
+ if (dev->quirks & DW_I2S_QUIRK_NO_BURST)
+ dev->play_dma_data.dt.maxburst = 1;
+ else
+ dev->play_dma_data.dt.maxburst = 16;
}
if (COMP1_RX_ENABLED(comp1))
{ idx2 = COMP2_RX_WORDSIZE_0(comp2);
@@ -722,7 +725,10 @@ static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev,
dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;
dev->capture_dma_data.dt.fifo_size = fifo_depth *
(fifo_width[idx2] >> 8);
- dev->capture_dma_data.dt.maxburst = 16;
+ if (dev->quirks & DW_I2S_QUIRK_NO_BURST)
+ dev->capture_dma_data.dt.maxburst = 1;
+ else
+ dev->capture_dma_data.dt.maxburst = 16;
}
return 0;
@@ -979,6 +985,8 @@ static int dw_i2s_probe(struct platform_device *pdev)
ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata);
} else
{ clk_id = "i2sclk";
+ if (of_get_property(pdev->dev.of_node, "no-burst", NULL))
+ dev->quirks |= DW_I2S_QUIRK_NO_BURST;
ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res);
}
if (ret < 0)
--
2.34.1
