On Wed, Sep 06, 2023 at 11:41:38AM +0200, Lorenzo Pieralisi wrote: > The GIC v3 specifications allow redistributors and ITSes interconnect > ports used to access memory to be wired up in a way that makes the > respective initiators/memory observers non-coherent. > > Add the standard dma-noncoherent property to the GICv3 bindings to > allow firmware to describe the redistributors/ITSes components and > interconnect ports behaviour in system designs where the redistributors > and ITSes are not coherent with the CPU. > > Signed-off-by: Lorenzo Pieralisi <lpieralisi@xxxxxxxxxx> > Cc: Rob Herring <robh@xxxxxxxxxx> > --- > .../bindings/interrupt-controller/arm,gic-v3.yaml | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml > index 39e64c7f6360..c9bc9aad93f1 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml > @@ -106,6 +106,12 @@ properties: > $ref: /schemas/types.yaml#/definitions/uint32 > maximum: 4096 > > + dma-noncoherent: > + description: > + Present if the GIC redistributors permit programming shareability > + and cacheability attributes but are connected to a non-coherent > + downstream interconnect. > + > msi-controller: > description: > Only present if the Message Based Interrupt functionality is > @@ -193,6 +199,12 @@ patternProperties: > compatible: > const: arm,gic-v3-its > > + dma-noncoherent: > + description: > + Present if the GIC ITS permits programming shareability and > + cacheability attributes but are connected to a non-coherent s/are/is Sorry, I will update the patch accordingly. Lorenzo > + downstream interconnect. > + > msi-controller: true > > "#msi-cells": > -- > 2.34.1 >
