On Thu, 31 Aug 2023 at 08:39, Varadarajan Narayanan <quic_varada@xxxxxxxxxxx> wrote: > > Add USB phy and controller nodes. > > Signed-off-by: Varadarajan Narayanan <quic_varada@xxxxxxxxxxx> > --- > v10: > usb@8a00000 -> usb@8af8800 > "make W=1 ARCH=arm64 -j 16 CHECK_DTBS=y DT_SCHEMA_FILES=qcom,ipq5332-usb-hsphy.yaml dtbs_check" passed > v9: > usb2@8a00000 -> usb@8a00000 > "make ARCH=arm64 -j 16 CHECK_DTBS=y DT_SCHEMA_FILES=qcom,ipq5332-usb-hsphy.yaml dtbs_check" passed > v6: > Remove clock names > Move the nodes to address sorted location > v5: > Use generic phy instead of usb-phy > 'make CHECK_DTBS=y DT_SCHEMA_FILES=qcom dtbs_check' passed > 'DT_CHECKER_FLAGS='-v -m' DT_SCHEMA_FILES=qcom dt_binding_check' passed > v4: > Change node name > Remove blank line > 'make CHECK_DTBS=y DT_SCHEMA_FILES=qcom qcom/ipq5332-rdp441.dtb' passed > v1: > Rename phy node > Change compatible from m31,ipq5332-usb-hsphy -> qcom,ipq5332-usb-hsphy > Remove 'qscratch' from phy node > Fix alignment and upper-case hex no.s > Add clock definition for the phy > Remove snps,ref-clock-period-ns as it is not used. dwc3_ref_clk_period() > in dwc3/core.c takes the frequency from ref clock and calculates fladj > as appropriate. > --- > arch/arm64/boot/dts/qcom/ipq5332.dtsi | 55 +++++++++++++++++++++++++++++++++++ > 1 file changed, 55 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > index 8bfc2db..6593865 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > @@ -145,6 +145,19 @@ > #size-cells = <1>; > ranges = <0 0 0 0xffffffff>; > > + usbphy0: phy@7b000 { > + compatible = "qcom,ipq5332-usb-hsphy"; > + reg = <0x0007b000 0x12c>; > + > + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; > + > + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; > + > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > qfprom: efuse@a4000 { > compatible = "qcom,ipq5332-qfprom", "qcom,qfprom"; > reg = <0x000a4000 0x721>; > @@ -290,6 +303,48 @@ > status = "disabled"; > }; > > + usb: usb@8af8800 { > + compatible = "qcom,ipq5332-dwc3", "qcom,dwc3"; > + reg = <0x08af8800 0x400>; > + > + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "hs_phy_irq"; > + > + clocks = <&gcc GCC_USB0_MASTER_CLK>, > + <&gcc GCC_SNOC_USB_CLK>, > + <&gcc GCC_USB0_SLEEP_CLK>, > + <&gcc GCC_USB0_MOCK_UTMI_CLK>; > + clock-names = "core", > + "iface", > + "sleep", > + "mock_utmi"; > + > + resets = <&gcc GCC_USB_BCR>; > + > + qcom,select-utmi-as-pipe-clk; > + > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + status = "disabled"; > + > + usb2_0_dwc: usb@8a00000 { Since we have just seen a patch series adding USB 3 support to ipq5332, we know that the host is not 2.0-only. Thus the `2_0` part of the label doesn't make sense. Could you please change the label to be just usb_dwc (or usb0_dwc)? > + compatible = "snps,dwc3"; > + reg = <0x08a00000 0xe000>; > + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; > + clock-names = "ref"; > + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; > + phy-names = "usb2-phy"; > + phys = <&usbphy0>; > + tx-fifo-resize; > + snps,is-utmi-l1-suspend; > + snps,hird-threshold = /bits/ 8 <0x0>; > + snps,dis_u2_susphy_quirk; > + snps,dis_u3_susphy_quirk; > + }; > + }; > + > intc: interrupt-controller@b000000 { > compatible = "qcom,msm-qgic2"; > reg = <0x0b000000 0x1000>, /* GICD */ > -- > 2.7.4 > -- With best wishes Dmitry