On non-ChromeOS boards the clock cannot be touched, so move it in the
chrome-common dtsi which is the only place where it's needed.
Signed-off-by: Luca Weiss <luca.weiss@xxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi | 5 +++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 --
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
index 8eb30aa226a2..6cfcec1eabd9 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
@@ -59,6 +59,11 @@ &pmk8350_pon {
status = "disabled";
};
+&qfprom {
+ clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
+ clock-names = "core";
+};
+
/*
* Chrome designs always boot from SPI flash hooked up to the qspi.
*
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 98a8d627a348..5c78038369fd 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -897,8 +897,6 @@ qfprom: efuse@784000 {
<0 0x00780000 0 0xa20>,
<0 0x00782000 0 0x120>,
<0 0x00786000 0 0x1fff>;
- clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
- clock-names = "core";
power-domains = <&rpmhpd SC7280_MX>;
#address-cells = <1>;
#size-cells = <1>;
--
2.42.0
