On Tue, 29 Aug 2023 11:18:58 -0700, Tanmay Shah wrote: > From: Radhey Shyam Pandey <radhey.shyam.pandey@xxxxxxx> > > Introduce bindings for TCM memory address space on AMD-xilinx Zynq > UltraScale+ platform. It will help in defining TCM in device-tree > and make it's access platform agnostic and data-driven. > > Tightly-coupled memories(TCMs) are low-latency memory that provides > predictable instruction execution and predictable data load/store > timing. Each Cortex-R5F processor contains two 64-bit wide 64 KB memory > banks on the ATCM and BTCM ports, for a total of 128 KB of memory. > > The TCM resources(reg, reg-names and power-domain) are documented for > each TCM in the R5 node. The reg and reg-names are made as required > properties as we don't want to hardcode TCM addresses for future > platforms and for zu+ legacy implementation will ensure that the > old dts w/o reg/reg-names works and stable ABI is maintained. > > It also extends the examples for TCM split and lockstep modes. > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xxxxxxx> > Signed-off-by: Tanmay Shah <tanmay.shah@xxxxxxx> > --- > > Changes in v4: > - Use address-cells and size-cells value 2 > - Modify ranges property as per new value of address-cells > and size-cells > - Modify child node "reg" property accordingly > - Remove previous ack for further review > > > .../remoteproc/xlnx,zynqmp-r5fss.yaml | 131 +++++++++++++++--- > 1 file changed, 113 insertions(+), 18 deletions(-) > Acked-by: Rob Herring <robh@xxxxxxxxxx>
