Without setting the parent for SCLK_USB480M the clock will use xin24m as
it's default parent.
While this is generally not an issue for the usb blocks to work, it becomes
an issue for RK3128 since SCLK_USB480M can be a parent for other HW blocks
(GPU, VPU, VIO). They never will choose this clock as their parent, because
it currently always runs at OSC frequency.
This sets usb480m_phy as SCLK_USB480M's parent, which now runs and outputs
the expected frequency of 480 MHz and the other blocks can choose
SCLK_USB480M as their parent if needed.
Signed-off-by: Alex Bee <knaerzche@xxxxxxxxx>
---
arch/arm/boot/dts/rockchip/rk3128.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index 119e89fef2a2..5590af6f42ad 100644
--- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
@@ -113,6 +113,8 @@ usb_host_ehci: usb@101c0000 {
reg = <0x101c0000 0x20000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST2>;
+ assigned-clocks = <&cru SCLK_USB480M>;
+ assigned-clock-parents = <&usb2phy>;
phys = <&usb2phy_host>;
phy-names = "usb";
status = "disabled";
@@ -123,6 +125,8 @@ usb_host_ohci: usb@101e0000 {
reg = <0x101e0000 0x20000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST2>;
+ assigned-clocks = <&cru SCLK_USB480M>;
+ assigned-clock-parents = <&usb2phy>;
phys = <&usb2phy_host>;
phy-names = "usb";
status = "disabled";
--
2.42.0
