i.MX8QM HSIO(High Speed IO) module has three instances of single lane SERDES PHYs, an instance of two lanes PCIe GEN3 controller, an instance of single lane PCIe GEN3 controller, as well as an instance of SATA 3.0 controller. The HSIO module can be configured as the following different usecases. 1 - A two lanes PCIea and a single lane SATA. 2 - A single lane PCIea, a single lane PCIeb and a single lane SATA. 3 - A two lanes PCIea, a single lane PCIeb. Add i.MX8Q PCIe PHY driver to support these different usecases, and had been verified on i.MX8QM and i.MX8QXP MEK boards. [PATCH v1 1/3] dt-bindings: phy: Add i.MX8QM PCIe PHY binding [PATCH v1 2/3] dt-bindings: phy: phy-imx8-pcie: Add binding for [PATCH v1 3/3] phy: freescale: imx8q-pcie: Add i.MX8Q PCIe PHY driver Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml | 70 ++++++++++- drivers/phy/freescale/Kconfig | 8 ++ drivers/phy/freescale/Makefile | 1 + drivers/phy/freescale/phy-fsl-imx8q-pcie.c | 562 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ include/dt-bindings/phy/phy-imx8-pcie.h | 7 ++ 5 files changed, 645 insertions(+), 3 deletions(-)
