Fix the "assigned-clock-rates" for each clock output in the
example based on Table 3. ("Output Source") in the 5P35023
datasheet(ie: {REF,SE1,SE2,SE3,DIFF1,DIFF2}).
While at it, replace clocks phandle in the example from x1_x2->x1 as
X2 is a different 32768 kHz crystal.
Suggested-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Fixes: a03d23f860eb ("dt-bindings: clock: Add Renesas versa3 clock generator bindings")
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
---
v3->v4:
* Dropped clock-output-names as there is no validation for it and people
can get it wrong.
* Updated commit header, description and example to reflect this change
* Retained Ack tag from Conor and Krzysztof as it is trivial change.
v2->v3:
* No change.
v1->v2:
* Updated commit description to make it clear it fixes
"assigned-clock-rates" in the example based on 5P35023 datasheet.
---
.../devicetree/bindings/clock/renesas,5p35023.yaml | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml
index 839648e753d4..8260af2a36db 100644
--- a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml
@@ -68,7 +68,7 @@ examples:
reg = <0x68>;
#clock-cells = <1>;
- clocks = <&x1_x2>;
+ clocks = <&x1>;
renesas,settings = [
80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
@@ -79,8 +79,8 @@ examples:
assigned-clocks = <&versa3 0>, <&versa3 1>,
<&versa3 2>, <&versa3 3>,
<&versa3 4>, <&versa3 5>;
- assigned-clock-rates = <12288000>, <25000000>,
- <12000000>, <11289600>,
- <11289600>, <24000000>;
+ assigned-clock-rates = <24000000>, <11289600>,
+ <11289600>, <12000000>,
+ <25000000>, <12288000>;
};
};
--
2.25.1
