Hi Uwe,
Gentle ping.
> Subject: RE: [PATCH v5 0/4] Add RZ/V2{M, MA} PWM driver support
>
> Hi Uwe,
>
> Gentle ping.
>
> Cheers,
> Biju
>
> > Subject: [PATCH v5 0/4] Add RZ/V2{M, MA} PWM driver support
> >
> > The RZ/V2{M, MA} PWM Timer (PWM) is composed of 16 channels. Linux is
> > only allowed access to channels 8 to 14 on RZ/V2M, while there is no
> > restriction for RZ/V2MA.
> >
> > The RZ/V2{M, MA} PWM Timer (PWM) supports the following functions:
> > * The PWM has 24-bit counters which operate at PWM_CLK (48 MHz).
> > * The frequency division ratio for internal counter operation is
> > selectable
> > as PWM_CLK divided by 1, 16, 256, or 2048.
> > * The period as well as the duty cycle is adjustable.
> > * The low-level and high-level order of the PWM signals can be inverted.
> > * The duty cycle of the PWM signal is selectable in the range from 0
> > to 100%.
> > * The minimum resolution is 20.83 ns.
> > * Three interrupt sources: Rising and falling edges of the PWM signal
> and
> > clearing of the counter
> > * Counter operation and the bus interface are asynchronous and both can
> > operate independently of the magnitude relationship of the respective
> > clock periods.
> >
> > v4->v5:
> > * rebased to pwm for-next.
> > * Sorted KConfig file
> > * Sorted Make file
> > * Updated copyright header 2022->2023.
> > * Updated limitation section.
> > * Replaced the variable chip->rzv2m_pwm in rzv2m_pwm_wait_delay()
> > * Replaced polarity logic as per HW manual dutycycle = Ton/Ton+Toff, so
> > eventhough native polarity is inverted from period point of view it is
> > correct.
> > * Updated logic for supporting 0% , 100% and remaining duty cycles.
> > * On config() replaced
> > pm_runtime_resume_and_get()->pm_runtime_get_sync()
> > * Counter is stopped while updating period/polarity to avoid glitches.
> > * Added error check for clk_prepare_enable()
> > * Introduced is_ch_enabled variable to cache channel enable status.
> > * clk_get_rate is called after enabling the clock and
> > clk_rate_exclusive_get()
> > * Added comment for delay
> > * Replaced 1000000000UL->NSEC_PER_SEC.
> > * Improved error handling in probe().
> > v3->v4:
> > * Documented the hardware properties in "Limitations" section
> > * Dropped the macros F2CYCLE_NSEC, U24_MASK and U24_MAX.
> > * Added RZV2M_PWMCYC_PERIOD macro for U24_MAX
> > * Dropped rzv2m_pwm_freq_div variable and started using 1 << (4 * i) for
> > calculating divider as it is power of 16.
> > * Reordered the functions to have rzv2m_pwm_config() directly before
> > rzv2m_pwm_apply().
> > * Improved the logic for calculating period and duty cycle in
> > config()
> > * Merged multiple RZV2M_PWMCTR register writes to a single write in
> > config()
> > * replaced pwm_is_enabled()->pwm->state.enabled
> > * Avoided assigning bit value as enum pwm_polarity instead used enum
> > constant.
> > * Fixed various issues in probe error path.
> > * Updated the logic for PWM cycle setting register
> > * A 100% duty cycle is only possible with PWMLOW > PWMCYC. So
> restricting
> > PWMCYC values < 0xffffff
> > * The native polarity of the hardware is inverted (i.e. it starts
> > with the
> > * low part). So switched the inversion bit handling.
> > v2->v3:
> > * Removed clock patch#1 as it is queued for 6.3 renesas-clk
> > * Added Rb tag from Geert for bindings and dt patches
> > * Added return code for rzv2m_pwm_get_state()
> > * Added comment in rzv2m_pwm_reset_assert_pm_disable()
> > v1->v2:
> > * Updated commit description
> > * Replaced pwm8_15_pclk->cperi_grpf
> > * Added reset entry R9A09G011_PWM_GPF_PRESETN
> > * Added Rb tag from Krzysztof for bindings and the keep the Rb tag as
> > the below changes are trivial
> > * Updated the description for APB clock
> > * Added resets required property
> > * Updated the example with resets property
> > * Replaced devm_reset_control_get_optional_shared-
> > >devm_reset_control_get_shared
> > * Added resets property in pwm nodes.
> >
> > Note:
> > Hardware manual for this IP can be found here
> > https://www.renesas.com/in/en/document/mah/rzv2m-users-manual-
> > hardware?language=en
> >
> > Biju Das (4):
> > dt-bindings: pwm: Add RZ/V2M PWM binding
> > pwm: Add support for RZ/V2M PWM driver
> > arm64: dts: renesas: r9a09g011: Add pwm nodes
> > arm64: dts: renesas: rzv2m evk: Enable pwm
> >
> > .../bindings/pwm/renesas,rzv2m-pwm.yaml | 90 ++++
> > .../boot/dts/renesas/r9a09g011-v2mevk2.dts | 70 +++
> > arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 98 ++++
> > drivers/pwm/Kconfig | 11 +
> > drivers/pwm/Makefile | 1 +
> > drivers/pwm/pwm-rzv2m.c | 451 ++++++++++++++++++
> > 6 files changed, 721 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/pwm/renesas,rzv2m-
> > pwm.yaml
> > create mode 100644 drivers/pwm/pwm-rzv2m.c
> >
> >
> > base-commit: 92554cdd428fce212d2a71a06939e7cab90f7c77
> > --
> > 2.25.1
