On 19/08/2023 05:17, Sam Protsenko wrote:
> Add USB controller and USB PHY controller nodes for Exynos850 SoC.
>
> The USB controller has next features:
> - Dual Role Device (DRD) controller
> - DWC3 compatible
> - Supports USB 2.0 host and USB 2.0 device interfaces
> - Supports full-speed (12 Mbps) and high-speed (480 Mbps) modes with
> USB device 2.0 interface
> - Supports on-chip USB PHY transceiver
> - Supports up to 16 bi-directional endpoints (that includes control
> endpoint 0)
> - Complies with xHCI 1.00 specification
>
> Only USB 2.0 is supported in Exynos850, so only UTMI+ PHY interface is
> specified in "phys" property (index 0) and PIPE3 is omitted (index 1).
>
> Signed-off-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx>
> ---
> arch/arm64/boot/dts/exynos/exynos850.dtsi | 30 +++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi
> index aa077008b3be..198d1dfcc672 100644
> --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi
> @@ -570,6 +570,36 @@ sysreg_cmgp: syscon@11c20000 {
> clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>;
> };
>
> + usbdrd: usb@13600000 {
> + compatible = "samsung,exynos850-dwusb3";
> + clocks = <&cmu_hsi CLK_GOUT_USB_BUS_EARLY_CLK>,
> + <&cmu_hsi CLK_GOUT_USB_REF_CLK>;
> + clock-names = "bus_early", "ref";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x13600000 0x10000>;
Please put ranges after compatible. I know that existing code does not
follow this convention, though.
> + status = "disabled";
> +
Best regards,
Krzysztof
