On 2023-08-15 14:59, Muhammed Efe Cetin wrote:
> Add sfc node to rk3588s.dtsi from downstream kernel.
>
> Signed-off-by: Muhammed Efe Cetin <efectn@xxxxxxxx>
> ---
> arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> index 5544f66c6ff4..a38a0158fce0 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> @@ -1424,6 +1424,19 @@ sata-port@0 {
> };
> };
>
> + sfc: spi@fe2b0000 {
> + compatible = "rockchip,sfc";
> + reg = <0x0 0xfe2b0000 0x0 0x4000>;
> + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
gic use 4 interrupt-cells, should be:
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
> + clock-names = "clk_sfc", "hclk_sfc";
> + assigned-clocks = <&cru SCLK_SFC>;
> + assigned-clock-rates = <100000000>;
You should not need to assign clock rate here, do it in your board dts
if you really must.
Regards,
Jonas
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> sdmmc: mmc@fe2c0000 {
> compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
> reg = <0x0 0xfe2c0000 0x0 0x4000>;
