On Tue, Aug 15, 2023 at 8:58 PM Fabio Estevam <festevam@xxxxxxxxx> wrote:
>
> Hi Adam,
>
> On Tue, Aug 15, 2023 at 8:11 PM Adam Ford <aford173@xxxxxxxxx> wrote:
> >
> > A previous patch to remove the Audio clocks from the main clock node
>
> Nit: Instead of referring to "A previous patch", it would be clearer
> to explicitly
> refer to the actual commit.
I tried to do that with the fixes tag below. Do you want me to
re-submit the patches with this changed? I was hoping to avoid
referencing the same patch and hash twice in the same commit message.
adam
>
> > was intended to force people to setup the audio PLL clocks per board
> > instead of having a common set of rates since not all boards may use
> > the various audio PLL clocks for audio devices.
> >
> > Unfortunately, with this parenting removed, the SDMA2 and SDMA3
> > clocks were slowed to 24MHz because the SDMA2/3 clocks are controlled
> > via the audio_blk_ctrl which is clocked from IMX8MP_CLK_AUDIO_ROOT,
> > and that clock is enabled by pgc_audio.
> >
> > Per the TRM, "The SDMA2/3 target frequency is 400MHz IPG and 400MHz
> > AHB, always 1:1 mode, to make sure there is enough throughput for all
> > the audio use cases."
> >
> > Instead of cluttering the clock node, place the clock rate and parent
> > information into the pgc_audio node.
> >
> > With the parenting and clock rates restored for IMX8MP_CLK_AUDIO_AHB,
> > and IMX8MP_CLK_AUDIO_AXI_SRC, it appears the SDMA2 and SDMA3 run at
> > 400MHz again.
> >
> > Fixes: 16c984524862 ("arm64: dts: imx8mp: don't initialize audio clocks from CCM node")
> > Signed-off-by: Adam Ford <aford173@xxxxxxxxx>
> > Reviewed-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
>
> Reviewed-by: Fabio Estevam <festevam@xxxxxxxxx>
