This patch serises are to add timer driver for the StarFive JH7110 RISC-V SoC. The first patch adds documentation to describe device tree bindings. The subsequent patch adds timer driver and support JH7110 SoC. The last patch adds device node about timer in JH7110 dts. This timer has four free-running 32 bit counters and runs in 24MHz clock on StarFive JH7110 SoC. And each channel(counter) triggers an interrupt when timeout. They support one-shot mode and continuous-run mode. Changes since v3: - Rebased on 6.5-rc6 - Dropped the useless enum names like 'JH7110_TIMER_CH_0'. - Dropped the platform data about JH7110 and used the register offsets directly. - Drroped the useless functions of clk_disable_unprepare(). v3: https://lore.kernel.org/all/20230627055313.252519-1-xingyu.wu@xxxxxxxxxxxxxxxx/ Changes since v2: - Rebased on 6.4-rc7. - Merged the header file into the c file. - Renamed the functions from 'starfive_' to 'jh7110_' - Used function 'clocksource_register_hz' instead of 'clocksource_mmio_init'. v2: https://lore.kernel.org/all/20230320135433.144832-1-xingyu.wu@xxxxxxxxxxxxxxxx/ Changes since v1: - Added description about timer and modified properties' description in dt-bindings. - Dropped the 'interrupt-names' and 'clock-frequency' in dt-bindings. - Renamed the functions and added 'starfive_' - Modified that the driver probe by platform bus. v1: https://lore.kernel.org/all/20221223094801.181315-1-xingyu.wu@xxxxxxxxxxxxxxxx/ Xingyu Wu (3): dt-bindings: timer: Add timer for StarFive JH7110 SoC clocksource: Add JH7110 timer driver riscv: dts: jh7110: starfive: Add timer node .../bindings/timer/starfive,jh7110-timer.yaml | 96 ++++ MAINTAINERS | 7 + arch/riscv/boot/dts/starfive/jh7110.dtsi | 20 + drivers/clocksource/Kconfig | 11 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-jh7110.c | 415 ++++++++++++++++++ 6 files changed, 550 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml create mode 100644 drivers/clocksource/timer-jh7110.c -- 2.25.1
