On 12/08/2023 16:25, Gowthami Thiagarajan wrote: > Add binding documentation for Marvell Odyssey LLC-TAD performance > monitor unit > > Signed-off-by: Gowthami Thiagarajan <gthiagarajan@xxxxxxxxxxx> > --- > > v1->v2 > - Changed DT binding file name to match with compatible > - Added respective document in MAINTAINERS > > .../perf/marvell,odyssey-tad-pmu.yaml | 63 +++++++++++++++++++ > MAINTAINERS | 1 + > 2 files changed, 64 insertions(+) > create mode 100644 Documentation/devicetree/bindings/perf/marvell,odyssey-tad-pmu.yaml > > diff --git a/Documentation/devicetree/bindings/perf/marvell,odyssey-tad-pmu.yaml b/Documentation/devicetree/bindings/perf/marvell,odyssey-tad-pmu.yaml > new file mode 100644 > index 000000000000..a1b9ee71e5f7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/perf/marvell,odyssey-tad-pmu.yaml > @@ -0,0 +1,63 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/perf/marvell,odyssey-tad-pmu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Marvell Odyssey LLC-TAD performance monitor > + > +maintainers: > + - Gowthami Thiagarajan <gthiagarajan@xxxxxxxxxxx> > + > +description: | > + The Tag-and-Data units (TADs) maintain coherence and contain CN10K > + shared on-chip last level cache (LLC). The tad pmu measures the > + performance of last-level cache. Each tad pmu supports up to eight > + counters. > + > + The DT setup comprises of number of tad blocks, the sizes of pmu > + regions, tad blocks and overall base address of the HW. > + > +properties: > + compatible: > + const: marvell,odyssey-tad-pmu > + > + reg: > + maxItems: 1 > + > + marvell,tad-cnt: > + description: specifies the number of tads on the soc Why would it differ? Each SoC is the same, right? Like factory makes 1 million of the same SoCs, so tad-cnt is the same on each of them Please drop. > + $ref: /schemas/types.yaml#/definitions/uint32 > + > + marvell,tad-page-size: > + description: specifies the size of each tad page > + $ref: /schemas/types.yaml#/definitions/uint32 Same questions. > + > + marvell,tad-pmu-page-size: > + description: specifies the size of page that the pmu uses > + $ref: /schemas/types.yaml#/definitions/uint32 Same questions. > + > +required: > + - compatible > + - reg > + - marvell,tad-cnt > + - marvell,tad-page-size > + - marvell,tad-pmu-page-size > + > +additionalProperties: false > + > +examples: > + - | > + No need for blank line. > + tad { No clue what tad is, use some generic name. > + #address-cells = <2>; > + #size-cells = <2>; > + Best regards, Krzysztof
