On Sun, Aug 13, 2023 at 12:17:27PM +0800, Chen-Yu Tsai wrote:
> > Signed-off-by: John Watts <contact@xxxxxxxxxx>
> > ---
> > Changes in v3:
> > - Set default pinctrl for can controller
> > - Moved can nodes to proper location
> > - Moved can pins to proper location
> >
> > .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 34 +++++++++++++++++++
> > 1 file changed, 34 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> > index d59b4acf183a..24f2e70d5886 100644
> > --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> > +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> > @@ -52,6 +52,18 @@ pio: pinctrl@2000000 {
> > #gpio-cells = <3>;
> > #interrupt-cells = <3>;
> >
> > + /omit-if-no-ref/
>
> Just FYI this likely ends up doing nothing if you also have them
> referenced through a default pinctrl setting. They end up always
> referenced and always included. For the D1 series it looks like no
> peripheral has default pinctrl setting given.
>
> We can still keep it though. It would help when future chip variants
> specify different pinmuxes.
Oops, thanks for pointing that out. I'll try to avoid that mistake in future.
> The compatible string should be the first property. In other sunxi SoC dtsi
> files, we put the pinctrl just before the "status" property if it's present
> to specify a default pin muxing.
Oh that makes sense.
>
> I can fix it up while applying.
Please do!
> ChenYu
Thanks,
John.
