On 12.08.2023 13:24, Adam Skladowski wrote: > Add PLL configuration for MSM8976 SoC, this SoC offers 3 HFPLL. > Small cluster offers two presets for 652-902Mhz range and 902Mhz-1.47Ghz. > For simplicity only add second range as smaller frequencies can be obtained > via apcs divider or safe parent this also saves us > a hassle of reconfiguring VCO bit and config_val. > A72 and CCI cluster only use single frequency range with their > outputs/post_dividers/vco_bits being static. > > Signed-off-by: Adam Skladowski <a39.skl@xxxxxxxxx> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> Konrad
