bootph-all as phase tag was added to dt-schema
(dtschema/schemas/bootph.yaml) to cover U-Boot challenges with DT.
That's why add it also to Linux to be aligned with bootloader requirement.
On TI K3 J784S4 SoC, only secure_proxy_mcu and secure_proxy_sa3 nodes are
exclusively used by R5 bootloader, rest of the dts nodes with bootph-* are
used by later boot stages also.
And secure_proxy_mcu and secure_proxy_sa3 are disabled in kernel device
tree, and will be only enabled in R5 bootloader device tree.
So, bootph-pre-ram for secure_proxy_mcu and secure_proxy_sa3 will be
added in R5 bootloader device tree only.
Add bootph-all for all other nodes that are used in the bootloader on
K3 J784S4 SoC, and bootph-pre-ram is not needed specifically for any node
in kernel dts.
Signed-off-by: Apurva Nandan <a-nandan@xxxxxx>
---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 2 ++
arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 9 +++++++++
arch/arm64/boot/dts/ti/k3-j784s4.dtsi | 2 ++
3 files changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index a04c44708a09..65eca0990300 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -670,6 +670,7 @@ main_sdhci1: mmc@4fb0000 {
};
main_navss: bus@30000000 {
+ bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@@ -705,6 +706,7 @@ main_udmass_inta: msi-controller@33d00000 {
};
secure_proxy_main: mailbox@32c00000 {
+ bootph-all;
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
index 740ee794d7b9..a394bef093b6 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
@@ -7,6 +7,7 @@
&cbass_mcu_wakeup {
sms: system-controller@44083000 {
+ bootph-all;
compatible = "ti,k2g-sci";
ti,host-id = <12>;
@@ -19,22 +20,26 @@ sms: system-controller@44083000 {
reg = <0x00 0x44083000 0x00 0x1000>;
k3_pds: power-controller {
+ bootph-all;
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
};
k3_clks: clock-controller {
+ bootph-all;
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
k3_reset: reset-controller {
+ bootph-all;
compatible = "ti,sci-reset";
#reset-cells = <2>;
};
};
chipid@43000014 {
+ bootph-all;
compatible = "ti,am654-chipid";
reg = <0x00 0x43000014 0x00 0x4>;
};
@@ -161,6 +166,7 @@ mcu_timer0: timer@40400000 {
};
mcu_timer1: timer@40410000 {
+ bootph-all;
compatible = "ti,am654-timer";
reg = <0x00 0x40410000 0x00 0x400>;
interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
@@ -442,6 +448,7 @@ mcu_spi2: spi@40320000 {
};
mcu_navss: bus@28380000 {
+ bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@@ -451,6 +458,7 @@ mcu_navss: bus@28380000 {
dma-ranges;
mcu_ringacc: ringacc@2b800000 {
+ bootph-all;
compatible = "ti,am654-navss-ringacc";
reg = <0x00 0x2b800000 0x00 0x400000>,
<0x00 0x2b000000 0x00 0x400000>,
@@ -465,6 +473,7 @@ mcu_ringacc: ringacc@2b800000 {
};
mcu_udmap: dma-controller@285c0000 {
+ bootph-all;
compatible = "ti,j721e-navss-mcu-udmap";
reg = <0x00 0x285c0000 0x00 0x100>,
<0x00 0x2a800000 0x00 0x40000>,
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi
index 8b5974d92e33..4398c3a463e1 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi
@@ -228,6 +228,7 @@ pmu: pmu {
};
cbass_main: bus@100000 {
+ bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@@ -263,6 +264,7 @@ cbass_main: bus@100000 {
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
cbass_mcu_wakeup: bus@28380000 {
+ bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
--
2.34.1
