> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
> Sent: Tuesday, August 8, 2023 1:58 PM
> To: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>; Sylwester
> Nawrocki <s.nawrocki@xxxxxxxxxxx>; Tomasz Figa
> <tomasz.figa@xxxxxxxxx>; Chanwoo Choi <cw00.choi@xxxxxxxxxxx>; Alim
> Akhtar <alim.akhtar@xxxxxxxxxxx>; Michael Turquette
> <mturquette@xxxxxxxxxxxx>; Stephen Boyd <sboyd@xxxxxxxxxx>; Rob
> Herring <robh+dt@xxxxxxxxxx>; Conor Dooley <conor+dt@xxxxxxxxxx>;
> linux-samsung-soc@xxxxxxxxxxxxxxx; linux-clk@xxxxxxxxxxxxxxx; linux-arm-
> kernel@xxxxxxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx;
> devicetree@xxxxxxxxxxxxxxx
> Subject: [PATCH 03/11] clk: samsung: exynos5250: do not define number of
> clocks in bindings
>
> Number of clocks supported by Linux drivers might vary - sometimes we add
> new clocks, not exposed previously. Therefore this number of clocks
should
> not be in the bindings, because otherwise we should not change it.
>
> Define number of clocks per each clock controller inside the driver
directly.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
> ---
Reviewed-by: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>
> drivers/clk/samsung/clk-exynos5250.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-
> exynos5250.c
> index 92fb09922f28..8ebe6155d8b7 100644
> --- a/drivers/clk/samsung/clk-exynos5250.c
> +++ b/drivers/clk/samsung/clk-exynos5250.c
> @@ -100,6 +100,9 @@
> #define PWR_CTRL2_CORE2_UP_RATIO (1 << 4)
> #define PWR_CTRL2_CORE1_UP_RATIO (1 << 0)
>
> +/* NOTE: Must be equal to the last clock ID increased by one */
> +#define CLKS_NR
> (CLK_MOUT_VPLLSRC + 1)
> +
> /* list of PLLs to be registered */
> enum exynos5250_plls {
> apll, mpll, cpll, epll, vpll, gpll, bpll, @@ -797,7 +800,7 @@ static
void
> __init exynos5250_clk_init(struct device_node *np)
> panic("%s: unable to determine soc\n", __func__);
> }
>
> - ctx = samsung_clk_init(NULL, reg_base, CLK_NR_CLKS);
> + ctx = samsung_clk_init(NULL, reg_base, CLKS_NR);
> hws = ctx->clk_data.hws;
>
> samsung_clk_of_register_fixed_ext(ctx,
> exynos5250_fixed_rate_ext_clks,
> --
> 2.34.1
