The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and
LPDDR4/4X memory interfaces. It has four programmable NoC interface
ports and is designed to handle multiple streams of traffic.
Optional external interface reliability include ECC error
detection/correction and command address parity.
Adding edac support for DDR Memory controller.
Changes in v8:
remove disabling all interrupts
Changes in v7:
Update the subject to add memory-controllers instead of edac
Update the message
Clear status after handling the error
At probe disable all the unrequested interrupts.
Alphabetically sorted diff
Rename unCorrectable to uncorrectable
Use mask0 for GENMASK(0,5)
Add a processbit function
Changes in v6:
Fix the warn.
Changes in v5:
Update subject
Changes in v4:
Update the reviewed by tag
Update the subject
rename the driver file.
fix the debugfs file.
fix unneeded capitalisation.
refactor code
Changes in v3:
Rebased and resent.
Changes in v2:
remove edac from compatible
Update the description
update the ddrmc_base and ddrmc_noc_base names
Update a missed out file
remove edac from compatible name
rename ddrmc_noc_base and ddrmc_base
Shubhrajyoti Datta (2):
dt-bindings: memory-controllers: Add support for Xilinx Versal EDAC
for DDRMC
EDAC/versal: Add a Xilinx Versal memory controller driver
.../xlnx,versal-ddrmc-edac.yaml | 57 +
MAINTAINERS | 7 +
drivers/edac/Kconfig | 11 +
drivers/edac/Makefile | 1 +
drivers/edac/versal_edac.c | 1065 +++++++++++++++++
include/linux/firmware/xlnx-zynqmp.h | 12 +
6 files changed, 1153 insertions(+)
create mode 100644 Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml
create mode 100644 drivers/edac/versal_edac.c
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2.17.1
