Add a new structure wdt_params to describe the watchdog difference of different chips. Signed-off-by: Huqiang Qin <huqiang.qin@xxxxxxxxxxx> --- V1 -> V2: Rename rst_shift to rst and use the BIT() macro to build its initial value. drivers/watchdog/meson_gxbb_wdt.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/watchdog/meson_gxbb_wdt.c b/drivers/watchdog/meson_gxbb_wdt.c index 35d80cb39856..18180d91543e 100644 --- a/drivers/watchdog/meson_gxbb_wdt.c +++ b/drivers/watchdog/meson_gxbb_wdt.c @@ -22,7 +22,6 @@ #define GXBB_WDT_CTRL_CLKDIV_EN BIT(25) #define GXBB_WDT_CTRL_CLK_EN BIT(24) -#define GXBB_WDT_CTRL_EE_RESET BIT(21) #define GXBB_WDT_CTRL_EN BIT(18) #define GXBB_WDT_CTRL_DIV_MASK (BIT(18) - 1) @@ -45,6 +44,10 @@ struct meson_gxbb_wdt { struct clk *clk; }; +struct wdt_params { + u32 rst; +}; + static int meson_gxbb_wdt_start(struct watchdog_device *wdt_dev) { struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev); @@ -140,8 +143,12 @@ static const struct dev_pm_ops meson_gxbb_wdt_pm_ops = { SET_SYSTEM_SLEEP_PM_OPS(meson_gxbb_wdt_suspend, meson_gxbb_wdt_resume) }; +static const struct wdt_params gxbb_params = { + .rst = BIT(21), +}; + static const struct of_device_id meson_gxbb_wdt_dt_ids[] = { - { .compatible = "amlogic,meson-gxbb-wdt", }, + { .compatible = "amlogic,meson-gxbb-wdt", .data = &gxbb_params, }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, meson_gxbb_wdt_dt_ids); @@ -150,6 +157,7 @@ static int meson_gxbb_wdt_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct meson_gxbb_wdt *data; + struct wdt_params *params; u32 ctrl_reg; data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); @@ -164,6 +172,8 @@ static int meson_gxbb_wdt_probe(struct platform_device *pdev) if (IS_ERR(data->clk)) return PTR_ERR(data->clk); + params = (struct wdt_params *)of_device_get_match_data(dev); + platform_set_drvdata(pdev, data); data->wdt_dev.parent = dev; @@ -191,7 +201,7 @@ static int meson_gxbb_wdt_probe(struct platform_device *pdev) /* Setup with 1ms timebase */ ctrl_reg |= ((clk_get_rate(data->clk) / 1000) & GXBB_WDT_CTRL_DIV_MASK) | - GXBB_WDT_CTRL_EE_RESET | + params->rst | GXBB_WDT_CTRL_CLK_EN | GXBB_WDT_CTRL_CLKDIV_EN; -- 2.37.1