On Tue, 1 Aug 2023 11:33:39 +0200
Andrew Lunn <andrew@xxxxxxx> wrote:
> On Wed, Jul 26, 2023 at 05:02:04PM +0200, Herve Codina wrote:
> > Available timeslots masks define timeslots available for the related
> > channel. These timeslots are defined by the QMC binding.
> >
> > Timeslots used are initialized to available timeslots but can be a
> > subset of available timeslots.
> > This prepares the dynamic timeslots management (ie. changing timeslots
> > at runtime).
> >
> > Signed-off-by: Herve Codina <herve.codina@xxxxxxxxxxx>
> > ---
> > drivers/soc/fsl/qe/qmc.c | 8 ++++++--
> > 1 file changed, 6 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
> > index 2d2a9d88ba6c..21ad7e79e7bd 100644
> > --- a/drivers/soc/fsl/qe/qmc.c
> > +++ b/drivers/soc/fsl/qe/qmc.c
> > @@ -177,7 +177,9 @@ struct qmc_chan {
> > struct qmc *qmc;
> > void __iomem *s_param;
> > enum qmc_mode mode;
> > + u64 tx_ts_mask_avail;
> > u64 tx_ts_mask;
> > + u64 rx_ts_mask_avail;
> > u64 rx_ts_mask;
>
> Is this for E1? So there is a maximum of 32 slots? A u32 would be
> sufficient i think?
>
The QMC can use up to 64 slots. So masks related to the QMC are on 64bits.
These masks are not specific to the E1 framer but really related to the QMC
capabilities.
Regards,
Hervé
