On 27/07/2023 18:29, Duje Mihanović wrote: > Add dt bindings and documentation for the Marvell PXA1908 clock > controller. > > Signed-off-by: Duje Mihanović <duje.mihanovic@xxxxxxxx> > --- ... > +/* apb (apbc) peripherals */ > +#define PXA1908_CLK_UART0 1 > +#define PXA1908_CLK_UART1 2 > +#define PXA1908_CLK_GPIO 3 > +#define PXA1908_CLK_PWM0 4 > +#define PXA1908_CLK_PWM1 5 > +#define PXA1908_CLK_PWM2 6 > +#define PXA1908_CLK_PWM3 7 > +#define PXA1908_CLK_SSP0 8 > +#define PXA1908_CLK_SSP1 9 > +#define PXA1908_CLK_IPC_RST 10 > +#define PXA1908_CLK_RTC 11 > +#define PXA1908_CLK_TWSI0 12 > +#define PXA1908_CLK_KPC 13 > +#define PXA1908_CLK_SWJTAG 17 > +#define PXA1908_CLK_SSP2 20 > +#define PXA1908_CLK_TWSI1 25 > +#define PXA1908_CLK_THERMAL 28 > +#define PXA1908_CLK_TWSI3 29 > +#define PXA1908_APBC_NR_CLKS 48 > + > +/* apb (apbcp) peripherals */ > +#define PXA1908_CLK_UART2 7 > +#define PXA1908_CLK_TWSI2 10 > +#define PXA1908_CLK_AICER 14 > +#define PXA1908_APBCP_NR_CLKS 14 > + > +/* axi (apmu) peripherals */ > +#define PXA1908_CLK_CCIC1 9 > +#define PXA1908_CLK_ISP 14 Why do you have gaps between IDs? The clock IDs are supposed to be continuous, otherwise it is not an ID. > +#define PXA1908_CLK_GATE_CTRL 16 Best regards, Krzysztof
