On Mon, Jul 24, 2023 at 04:48:43PM +0530, Shubhrajyoti Datta wrote:
> Convert the xlnx,zynqmp-clk.txt to yaml.
> versal-clk.yaml already exists that's why ZynqMP is converted and
> merged.
>
> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xxxxxxx>
>
> ---
>
> Changes in v3:
> Update the min and maxitems
>
> Changes in v2:
> add enum in compatible
> fix the description
> add constraints for clocks
> name the clock-controller1 to clock-controller
>
> .../bindings/clock/xlnx,versal-clk.yaml | 78 ++++++++++++++++---
> .../bindings/clock/xlnx,zynqmp-clk.txt | 63 ---------------
> 2 files changed, 69 insertions(+), 72 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
> index e9cf747bf89b..deebbfd084e8 100644
> --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
> +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
> @@ -19,7 +19,9 @@ select: false
> properties:
> compatible:
> oneOf:
> - - const: xlnx,versal-clk
> + - enum:
> + - xlnx,versal-clk
> + - xlnx,zynqmp-clk
> - items:
> - enum:
> - xlnx,versal-net-clk
> @@ -31,16 +33,12 @@ properties:
> clocks:
> description: List of clock specifiers which are external input
> clocks to the given clock controller.
> - items:
> - - description: reference clock
> - - description: alternate reference clock
> - - description: alternate reference clock for programmable logic
> + minItems: 3
> + maxItems: 7
This doesn't seem right to me. The original binding requires 5 clock
inputs, but this will relax it such that only three are needed, no?
You'll need to set constraints on a per compatible basis.
Thanks,
Conor.
> clock-names:
> - items:
> - - const: ref
> - - const: alt_ref
> - - const: pl_alt_ref
> + minItems: 3
> + maxItems: 7
>
> required:
> - compatible
> @@ -50,6 +48,59 @@ required:
>
> additionalProperties: false
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - xlnx,versal-clk
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: reference clock
> + - description: alternate reference clock
> + - description: alternate reference clock for programmable logic
> +
> + clock-names:
> + items:
> + - const: ref
> + - const: alt_ref
> + - const: pl_alt_ref
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - xlnx,zynqmp-clk
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: PS reference clock
> + - description: reference clock for video system
> + - description: alternative PS reference clock
> + - description: auxiliary reference clock
> + - description: transceiver reference clock
> + - description: (E)MIO clock source (Optional clock)
> + - description: GEM emio clock (Optional clock)
> + - description: Watchdog external clock (Optional clock)
> +
> + clock-names:
> + items:
> + - const: pss_ref_clk
> + - const: video_clk
> + - const: pss_alt_ref_clk
> + - const: aux_ref_clk
> + - const: gt_crx_ref_clk
> + - pattern: "^mio_clk[00-77]+.*$"
> + - pattern: "gem[0-3]+_emio_clk.*$"
> + - pattern: "swdt[0-1]+_ext_clk.*$"
> +
> examples:
> - |
> firmware {
> @@ -64,4 +115,13 @@ examples:
> };
> };
> };
> +
> + clock-controller {
> + #clock-cells = <1>;
> + compatible = "xlnx,zynqmp-clk";
> + clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
> + <&aux_ref_clk>, <>_crx_ref_clk>;
> + clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
> + "aux_ref_clk", "gt_crx_ref_clk";
> + };
> ...
> diff --git a/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt b/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt
> deleted file mode 100644
> index 391ee1a60bed..000000000000
> --- a/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt
> +++ /dev/null
> @@ -1,63 +0,0 @@
> ---------------------------------------------------------------------------
> -Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
> -Zynq MPSoC firmware interface
> ---------------------------------------------------------------------------
> -The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
> -tree. It reads required input clock frequencies from the devicetree and acts
> -as clock provider for all clock consumers of PS clocks.
> -
> -See clock_bindings.txt for more information on the generic clock bindings.
> -
> -Required properties:
> - - #clock-cells: Must be 1
> - - compatible: Must contain: "xlnx,zynqmp-clk"
> - - clocks: List of clock specifiers which are external input
> - clocks to the given clock controller. Please refer
> - the next section to find the input clocks for a
> - given controller.
> - - clock-names: List of clock names which are exteral input clocks
> - to the given clock controller. Please refer to the
> - clock bindings for more details.
> -
> -Input clocks for zynqmp Ultrascale+ clock controller:
> -
> -The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock
> -inputs. These required clock inputs are:
> - - pss_ref_clk (PS reference clock)
> - - video_clk (reference clock for video system )
> - - pss_alt_ref_clk (alternative PS reference clock)
> - - aux_ref_clk
> - - gt_crx_ref_clk (transceiver reference clock)
> -
> -The following strings are optional parameters to the 'clock-names' property in
> -order to provide an optional (E)MIO clock source:
> - - swdt0_ext_clk
> - - swdt1_ext_clk
> - - gem0_emio_clk
> - - gem1_emio_clk
> - - gem2_emio_clk
> - - gem3_emio_clk
> - - mio_clk_XX # with XX = 00..77
> - - mio_clk_50_or_51 #for the mux clock to gem tsu from 50 or 51
> -
> -
> -Output clocks are registered based on clock information received
> -from firmware. Output clocks indexes are mentioned in
> -include/dt-bindings/clock/xlnx-zynqmp-clk.h.
> -
> --------
> -Example
> --------
> -
> -firmware {
> - zynqmp_firmware: zynqmp-firmware {
> - compatible = "xlnx,zynqmp-firmware";
> - method = "smc";
> - zynqmp_clk: clock-controller {
> - #clock-cells = <1>;
> - compatible = "xlnx,zynqmp-clk";
> - clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>;
> - clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
> - };
> - };
> -};
> --
> 2.17.1
>
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