On Mon, Jul 24, 2023 at 07:50:28PM +0530, Mayuresh Chitale wrote:
> Add an entry for the Smstateen extension to the riscv,isa-extensions
> property.
>
> Signed-off-by: Mayuresh Chitale <mchitale@xxxxxxxxxxxxxxxx>
> Reviewed-by: Andrew Jones <ajones@xxxxxxxxxxxxxxxx>
Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
Thanks,
Conor.
> ---
> Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index cc1f546fdbdc..36ff6749fbba 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -128,6 +128,12 @@ properties:
> changes to interrupts as frozen at commit ccbddab ("Merge pull
> request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
>
> + - const: smstateen
> + description: |
> + The standard Smstateen extension for controlling access to CSRs
> + added by other RISC-V extensions in H/S/VS/U/VU modes and as
> + ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
> +
> - const: ssaia
> description: |
> The standard Ssaia supervisor-level extension for the advanced
> --
> 2.34.1
>
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