This patch adds a binding that describes the Rockchip usb PHYs
found on Rockchip SoCs usb interface.
Signed-off-by: Yunzhi Li <lyz@xxxxxxxxxxxxxx>
---
Changes in v6: None
Changes in v5:
- Adjust entry order of example devicetree node in document.
Changes in v4:
- Updata description for phy device tree subnode.
Changes in v3: None
.../devicetree/bindings/phy/rockchip-usb-phy.txt | 32 ++++++++++++++++++++++
1 file changed, 32 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
new file mode 100644
index 0000000..e9500d9
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
@@ -0,0 +1,32 @@
+ROCKCHIP USB2 PHY
+
+Required properties:
+ - compatible: rockchip,rk3288-usb-phy
+ - rockchip,grf : phandle to the syscon managing the "general
+ register files"
+ - #phy-cells: should be 1
+ - #address-cells: should be 1
+ - #size-cells: should be 0
+
+Sub-nodes:
+Each PHY should be represented as a sub-node.
+
+Sub-nodes
+required properties:
+- reg: the PHY number
+ "0" - PHY connect to OTG controller
+ "1" - PHY connect to HOST0 controller
+ "2" - PHY connect to HOST1 controller
+
+Optional Properties:
+- clocks : phandle + clock specifier for the phy clocks
+
+Example:
+
+usbphy: phy {
+ compatible = "rockchip,rk3288-usb-phy";
+ rockchip,grf = <&grf>;
+ #phy-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+};
--
2.0.0
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