On Fri, Jul 21, 2023 at 10:16:44AM +0200, AngeloGioacchino Del Regno wrote: > Il 20/07/23 22:07, Nícolas F. R. A. Prado ha scritto: > > The DSU PMU allows monitoring performance events in the DSU cluster, > > which is done by configuring and reading back values from the DSU PMU > > system registers. However, for write-access to be allowed by ELs lower > > than EL3, the EL3 firmware needs to update the setting on the ACTLR3_EL3 > > register, as it is disallowed by default. > > Typo: ACTLR_EL2, ACTLR_EL3 bit 12 must be set if SCR.NS is 1; > ACTLR_EL3 bit 12 must be set if SCR.NS is 0. > > On MT8195 Chromebooks, SCR.NS is 1 - hence ACTLR_EL2/EL3 must have BIT(12) set, > but at least ACTLR_EL2 doesn't have it set. > > I haven't verified EL3, but that doesn't matter, since both need to be set. The kernel is running at EL2 (as I verified from CurrentEL), so only ACTLR_EL3 needs to be set. ACTLR_EL2 controls whether EL1 can write to the register (in non-secure mode) [1], which doesn't matter in this case. [1] https://developer.arm.com/documentation/101430/r1p2/Register-descriptions/AArch64-system-registers/ACTLR-EL2--Auxiliary-Control-Register--EL2 Thanks, Nícolas
